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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. BQ25703A sluscu1 ? may 2017 BQ25703A i2c multi-chemistry battery buck-boost charge controller with system power monitor and processor hot monitor 1 1 features 1 ? charge 1- to 4-cell battery from wide range of input sources ? 3.5-v to 24-v input operating voltage ? supports usb2.0, usb 3.0, usb 3.1 (type c), and usb_pd input current settings ? seamless transition between buck and boost operation ? input current and voltage regulation (idpm and vdpm) against source overload ? power/current monitor for cpu throttling ? comprehensive prochot profile, imvp8 compliant ? input and battery current monitor ? system power monitor, imvp8 compliant ? narrow-vdc (nvdc) power path management ? instant-on with no battery or deeply discharged battery ? battery supplements system when adapter is fully-loaded ? ideal diode operation in supplement mode ? power up usb port from battery (usb otg) ? output 4.48-v to 20.8-v compatible with usb pd ? output current limit up to 6.35 a ? 800-khz or 1.2-mhz programmable switching frequency for 1- h to 2.2- h low profile inductor ? host control interface for flexible system configuration ? i2c (BQ25703A) port for optimal system performance and status reporting ? hardware pin to set input current limit without ec control ? high accuracy regulation and monitor ? 0.5% charge voltage regulation ? 2% input/charge current regulation ? 2% input/charge current monitor ? 5% power monitor ? safety ? thermal shutdown ? input, system, battery overvoltage protection ? mosfet inductor overcurrent protection ? low battery quiescent current ? input current optimizer (ico) to extract max input power ? charge any battery chemistry: li+, lifepo4, nicd, nimh, lead acid ? package: 32-pin 4 4 wqfn 2 applications ? drones, bluetooth speakers, ip cameras, detachable, and tablet pcs and power bank ? industrial and medical equipment ? portable equipment with rechargeable batteries 3 description the BQ25703A is a synchronous nvdc battery buck- boost charge controller, offering low component count, high efficiency solution for space-constraint, multi-chemistry battery charging applications. the nvdc-1 configuration allows the system to be regulated at battery voltage, but not drop below system minimum voltage. the system keeps operating even when the battery is completely discharged or removed. when load power exceeds input source rating, the battery goes into supplement mode and prevents the input source from being overloaded. the BQ25703A charges battery from a wide range of input sources including usb adapter, high voltage usb pd sources and traditional adapters. device information (1) part number package body size (nom) BQ25703A wqfn (32) 4.00 mm 4.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. application diagram BQ25703A acn vbus hidrv1 srn vsys batt (1s-4s) btst1btst2 lodrv1 sw1 sw2 lodrv2 hidrv2 srp /batdrv acp sys host (703 i2c) q1 q2 q3 q4 adapter 3.5v 24v i2c iadpt, ibat, psys, prochot copyright ? 2017, texas instruments incorporated productfolder ordernow technical documents tools & software support &community
2 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 description (continued) ........................................ 3 6 pin configuration and functions ......................... 4 7 specifications ......................................................... 7 7.1 absolute maximum ratings ...................................... 7 7.2 esd ratings ............................................................ 7 7.3 recommended operating conditions ....................... 7 7.4 thermal information .................................................. 8 7.5 electrical characteristics ........................................... 8 7.6 timing requirements .............................................. 16 7.7 typical characteristics ........................................... 17 8 detailed description ............................................ 20 8.1 overview ................................................................ 20 8.2 functional block diagram ...................................... 21 8.3 feature description ................................................. 22 8.4 device functional modes ........................................ 28 8.5 programming .......................................................... 29 8.6 register map ........................................................... 32 9 application and implementation ........................ 66 9.1 application information .......................................... 66 9.2 typical application .................................................. 66 10 power supply recommendations ..................... 74 11 layout ................................................................... 75 11.1 layout guidelines ................................................. 75 11.2 layout example .................................................... 75 12 device and documentation support ................. 77 12.1 device support .................................................... 77 12.2 documentation support ....................................... 77 12.3 receiving notification of documentation updates 77 12.4 community resources .......................................... 77 12.5 trademarks ........................................................... 77 12.6 electrostatic discharge caution ............................ 77 12.7 glossary ................................................................ 77 13 mechanical, packaging, and orderable information ........................................................... 78 4 revision history date revision notes may 2017 * initial release.
3 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 5 description (continued) during power up, the charger sets converter to buck, boost or buck-boost configuration based on input source and battery conditions. the charger automatically transits among buck, boost and buck-boost configuration without host control. in the absence of an input source, the BQ25703A supports on-the-go (otg) function from 1- to 4-cell battery to generate 4.48 v to 20.8 v on vbus. during otg mode, the charger regulates output voltage and output current. the BQ25703A monitors adapter current, battery current and system power. the flexibly programmed prochot output goes directly to cpu for throttle back when needed.
4 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 6 pin configuration and functions rsn package 32-pin wqfn top view pin functions pin i/o description name number acn 2 pwr input current sense resistor negative input. the leakage on acp and acn are matched. the series resistors on the acp and acn pins are placed between sense resistor and filter cap. refer to application and implementation for acp/acn filter design. acp 3 pwr input current sense resistor positive input. the leakage on acp and acn are matched. the series resistors on the acp and acn pins are placed between sense resistor and filter cap. refer to application and implementation for acp/acn filter design. batdrv 21 o p-channel battery fet (batfet) gate driver output. it is shorted to vsys to turn off the batfet. it goes 10 v below vsys to fully turn on batfet. batfet is in linear mode to regulate vsys at minimum system voltage when battery is depleted. batfet is fully on during fast charge and supplement mode. btst1 30 pwr buck mode high side power mosfet driver power supply. connect a 0.047- f capacitor between sw1 and btst1. the bootstrap diode between regn and btst1 is integrated. btst2 25 pwr boost mode high side power mosfet driver power supply. connect a 0.047- f capacitor between sw2 and btst2. the bootstrap diode between regn and btst2 is integrated. cell_batpresz 18 i battery cell selection pin for 1 ? 4 cell battery setting. cell_batpresz pin is biased from vdda. cell_batpresz pin also sets sysovp threshold to 5 v for 1-cell, 12 v for 2-cell and 18.5 v for 3-cell. cell_batpresz pin is pulled below v cell_batpresz_fall to indicate battery removal. the device exits learn mode, and disables charge. reg0x 05/04() goes back to default. 32 sw1 9 ibat 1 vbus 24 hidrv2 31 hidrv1 10 psys 2 acn 23 sw2 30 btst1 11 prochot 3 acp 22 vsys 29 lodrv1 12 sda 4 chrg_ok 21 batdrv 28 regn 13 scl 5 en_otg 20 srp 27 pgnd 14 cmpin 6 ilim_hiz 19 srn 26 lodrv2 15 cmpout 7 vdda 18 cell_batpresz 25 btst2 16 comp1 8 iadpt 17 comp2 thermal pad
5 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o description name number chrg_ok 4 o open drain active high indicator to inform the system good power source is connected to the charger input. connect to the pullup rail via 10-k resistor. when vbus rises above 3.5v or falls below 24.5v, chrg_ok is high after 50ms deglitch time. when vbus is falls below 3.2 v or rises above 26 v, chrg_ok is low. cmpin 14 i input of independent comparator. the independent comparator compares the voltage sensed on cmpin pin to internal reference, and its output is on cmpout pin. internal reference, output polarity and deglitch time is selectable by i2c. with polarity high (reg0x30[6] = 1), place a resistor between cmpin and cmpout to program hysteresis. with polarity low (reg0x30[6] = 0), the internal hysteresis is 100 mv. if the independent comparator is not in use, tie cmpin to ground. cmpout 15 i open-drain output of independent comparator. place pullup resistor from cmpout to pullup supply rail. internal reference, output polarity and deglitch time are selectable by i2c. comp2 17 i buck boost converter compensation pin 2. refer to bq25700 evm schematic for comp2 pin rc network. comp1 16 i buck boost converter compensation pin 1. refer to bq25700 evm schematic for comp1 pin rc network. en_otg 5 i active high to enable otg mode. when en_otg pin is high and reg0x 35[4] is high, otg can be enabled, refer to usb on-the-go (otg) for details of how to enable otg function hidrv1 31 o buck mode high side power mosfet (q1) driver. connect to high side n-channel mosfet gate. hidrv2 24 o boost mode high side power mosfet(q4) driver. connect to high side n-channel mosfet gate. iadpt 8 o buffered adapter current output. v (iadp) = 20 or 40 (v (acp) ? v (acn) ). with ratio selectable in reg 0x00[4]. place a resistor from the iadpt pin to ground corresponding to inductor in use. for 2.2 h, the resistor is 137 k . place 100-pf or less ceramic decoupling capacitor from iadpt pin to ground. iadpt output voltage is clamped below 3.3 v. ibat 9 o buffered battery current selected by i2c. v (ibat) = 8 or 16 (v (srp) ? v (srn)) for charge current, or v (ibat) = 8 or 16 (v (srn) ? v (srp) ) for discharge current, with ratio selectable in reg 0x00[3]. place 100-pf or less ceramic decoupling capacitor from ibat pin to ground. this pin can be floating if not in use. its output voltage is clamped below 3.3 v. ilim_hiz 6 i input current limit input. program ilim_hiz voltage by connecting a resistor divider from supply rail to ilim_hiz pin to ground. the pin voltage is calculated as: v (ilim_hiz) = 1 v + 40 idpm rac, in which idpm is the target input current. the input current limit used by the charger is the lower setting of ilim_hiz pin and reg0x0f() and reg0x0e(). when the pin voltage is below 0.4 v, the device enters hi-z mode with low quiescent current. when the pin voltage is above 0.8 v, the device is out of hi-z mode. lodrv1 29 o buck mode low side power mosfet (q2) driver. connect to low side n-channel mosfet gate. lodrv2 26 o boost mode low side power mosfet (q3) driver. connect to low side n-channel mosfet gate. pgnd 27 gnd device power ground. prochot 11 o active low open drain output of processor hot indicator. it monitors adapter input current, battery discharge current, and system voltage. after any event in the prochot profile is triggered, a minimum 10-ms pulse is asserted. the pulse width is adjustable in reg 0x36[5:2]. psys 10 o current mode system power monitor. the output current is proportional to the total power from the adapter and battery. the gain is selectable through i2c. place resistor from psys to ground to generate output voltage. this pin can be floating if not in use. its output voltage is clamped below 3.3 v. place a capacitor in parallel with resistor for filtering. regn 28 pwr 6-v linear regulator output supplied from vbus or vsys. the ldo is active when vbus above v vbus_conven . connect a 2.2- or 3.3- f ceramic capacitor from regn to power ground. regn pin output is for power stage gate drive. scl 13 i i2c clock input. connect to clock line from the host controller or smart battery. connect a 10- k pullup resistor according to i2c specifications. sda 12 i/o i2c open-drain data i/o. connect to data line from the host controller or smart battery. connect a 10-k pullup resistor according to i2c specifications.
6 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o description name number srn 19 pwr charge current sense resistor negative input. srn pin is for battery voltage sensing as well. connect srn pin with optional 0.1- f ceramic capacitor to gnd for common-mode filtering. connect a 0.1- f ceramic capacitor from srp to srn to provide differential mode filtering. the leakage current on srp and srn are matched. for reverse battery plug-in protection, 10- series resistors are placed on srp and srn. srp 20 pwr charge current sense resistor positive input. connect 0.1- f ceramic capacitor from srp to srn to provide differential mode filtering. the leakage current on srp and srn are matched. for reverse battery plug-in protection, 10- series resistors are placed on srp and srn. connect srp pin with optional 0.1-uf ceramic capacitor to gnd for common-mode filtering. sw1 32 pwr buck mode high side power mosfet driver source. connect to the source of the high side n-channel mosfet. sw2 23 pwr boost mode high side power mosfet driver source. connect to the source of the high side n-channel mosfet. vbus 1 pwr charger input voltage. an input low pass filter of 1 and 0.47 f (minimum) is recommended. vdda 7 pwr internal reference bias pin. connect a 10- resistor from regn to vdda and a 1- f ceramic capacitor from vdda to power ground. vsys 22 pwr charger system voltage sensing. the system voltage regulation limit is programmed in reg0x05/04() and reg0x0d/0c(). thermal pad ? ? exposed pad beneath the ic. analog ground and power ground star-connected near the ic's ground. always solder thermal pad to the board, and have vias on the thermal pad plane connecting to power ground planes. it also serves as a thermal pad to dissipate the heat.
7 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to gnd if not specified. currents are positive into, negative out of the specified terminal. consult packaging section of the data book for thermal limitations and considerations of packages. 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit voltage srn, srp, acn, acp, vbus, vsys, batdrv ? 0.3 30 v sw1, sw2 ? 2.0 30 btst1, btst2, hidrv1, hidrv2 ? 0.3 36 lodrv1, lodrv2 (2% duty cycle) ? 4.0 7 hidrv1, hidrv2 (2% duty cycle) ? 4.0 36 sw1, sw2 (2% duty cycle) ? 4.0 30 sda, scl, regn, chrg_ok, cell_batpresz, ilim_hiz, lodrv1, lodrv2, vdda, comp1, comp2, cmpin, cmpout, en_otg ? 0.3 7 prochot ? 0.3 5.5 iadpt, ibat, psys ? 0.3 3.6 differential voltage btst1-sw1, btst2-sw2, hidrv1-sw1, hidrv2-sw2 ? 0.3 7 v srp-srn, acp-acn ? 0.5 0.5 junction temperature range, t j ? 40 155 c storage temperature, t stg ? 40 155 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 500 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit voltage acn, acp, vbus 0 24 v srn, srp, vsys, batdrv 0 19.2 sw1, sw2 ? 2 24 btst1, btst2, hidrv1, hidrv2 0 30 sda, scl, regn, chrg_ok, cell_batpresz, ilim_hiz, lodrv1, lodrv2, vdda, comp1, comp2, cmpin, cmpout 0 6.5 prochot 0 5.3 iadpt, ibat, psys 0 3.3 differential voltage btst1-sw1, btst2-sw2, hidrv1-sw1, hidrv2-sw2 0 6.5 v srp-srn, acp-acn ? 0.35 0.35 junction temperature, t j ? 40 125 c operating free-air temperature, t a ? 40 85 c
8 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 7.4 thermal information thermal metric (1) BQ25703A unit rsn (wqfn) 32 pins r ja junction-to-ambient thermal resistance 37.2 c/w r jc(top) junction-to-case (top) thermal resistance 26.1 c/w r jb junction-to-board thermal resistance 7.8 c/w jt junction-to-top characterization parameter 0.3 c/w jb junction-to-board characterization parameter 7.8 c/w r jc(bot) junction-to-case (bottom) thermal resistance 2.3 c/w 7.5 electrical characteristics over t j = ? 40 to 125 c (unless otherwise noted) parameter test conditions min typ max unit v input_op input voltage operating range 3.5 26 v regulation accuracy max system voltage regulation v sysmax_rng system voltage regulation, measured on v sys 1.024 19.2 v v sysmax_acc system voltage regulation accuracy (charge disable) reg0x 05/04() = 0x41a0h (16.800 v) v srn + 160 mv v ? 2% 2% reg0x 05/04() = 0x3130h (12.592 v) v srn + 160 mv v ? 2% 2% reg0x 05/04() = 0x20d0h (8.400 v) v srn + 160 mv v ? 3% 3% reg0x 05/04() = 0x1060h (4.192 v) v srn + 160 mv v ? 3% 3% minimum system voltage regulation v sysmin_rng system voltage regulation, measured on v sys 1.024 19.2 v v sysmin_reg_acc minimum system voltage regulation accuracy (charge enable, vbat below reg0x 0d/0c() setting) reg0x 0d/0c() = 0x3000h 12.288 v ? 2% 2% reg0x 0d/0c() = 0x2400h 9.216 v ? 2% 2% reg0x 0d/0c() = 0x1800h 6.144 v ? 3% 3% reg0x 0d/0c() = 0x0e00h 3.584 v ? 3% 4% charge voltage regulation v bat_rng battery voltage regulation 1.024 19.2 v v bat_reg_acc battery voltage regulation accuracy (charge enable) (0 c to 85 c) reg0x 05/04() = 0x41a0h 16.8 v ? 0.5% 0.5% reg0x 05/04() = 0x3130h 12.592 v ? 0.5% 0.5% reg0x 05/04() = 0x20d0h 8.4 v ? 0.6% 0.6% reg0x 05/04() = 0x1060h 4.192 v ? 1.1% 1.2%
9 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over t j = ? 40 to 125 c (unless otherwise noted) parameter test conditions min typ max unit charge current regulation in fast charge v ireg_chg_rng charge current regulation differential voltage range vireg_chg = vsrp ? vsrn 0 81.28 mv i chrg_reg_acc charge current regulation accuracy 10-m current sensing resistor, vbat above 0x 0d/0c() setting (0 c to 85 c) reg0x 03/02() = 0x1000h 4096 ma ? 3% 2% reg0x 03/02() = 0x0800h 2048 ma ? 4% 3% reg0x 03/02() = 0x0400h 1024 ma ? 5% 6% reg0x 03/02() = 0x0200h 512 ma ? 12% 12% charge current regulation in ldo mode i clamp pre-charge current clamp cell 2s-4s 384 ma cell 1 s, v srn < 3 v 384 ma cell 1 s, 3 v < v srn < vsysmin 2 a i prechrg_reg_acc pre-charge current regulation accuracy with 10- srp/srn series resistor, vbat below reg0x 0d/0c() setting (0 c to 85 c) reg0x 03/02() = 0x0180h 384 ma 2s-4s ? 15% 15% 1s ? 25% 25% reg0x 03/02() = 0x0100h 256 ma 2s-4s ? 20% 20% 1s ? 35% 35% reg0x 03/02() = 0x00c0h 192 ma 2s-4s ? 25% 25% 1s ? 50% 50% reg0x 03/02() = 0x0080h 128 ma 2s-4s ? 30% 30% i leak_srp_srn srp, srn leakage current mismatch (0 c to 85 c) ? 12 10 a input current regulation v ireg_dpm_rng input current regulation differential voltage range v ireg_dpm = v acp ? v acn 0.5 64 mv i dpm_reg_acc input current regulation accuracy ( ? 40 c to 105 c) with 10- acp/acn series resistor reg0x 0f/0e() = 0x4fffh 3820 4000 ma reg0x 0f/0e() = 0x3bffh 2830 3000 ma reg0x 0f/0e() = 0x1dffh 1350 1500 ma reg0x 0f/0e() = 0x09ffh 340 500 ma i leak_acp_acn acp, acn leakage current mismatch ? 16 10 a v ireg_dpm_rng_ilim voltage range for input current regulation 1 4 v i dpm_reg_acc_ilim input current regulation accuracy on ilim_hiz pin v ilim_hiz = 1 v + 40 idpm r ac , with 10- acp/acn series resistor v ilim_hiz = 2.6 v 3800 4000 4200 ma v ilim_hiz = 2.2 v 2800 3000 3200 ma v ilim_hiz = 1.6 v 1300 1500 1700 ma v ilim_hiz = 1.2 v 300 500 700 ma i leak_ilim i lim_hiz pin leakage ? 1 1 a input voltage regulation v ireg_dpm_rng input voltage regulation range voltage on vbus 3.2 19.52 v
10 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over t j = ? 40 to 125 c (unless otherwise noted) parameter test conditions min typ max unit v dpm_reg_acc input voltage regulation accuracy reg0x 07/06()=0x3c80h 18688 mv ? 2% 2% reg0x 07/06()=0x1e00h 10880 mv ? 2.5% 2.5% reg0x 07/06()=0x0500h 4480 mv ? 3% 5% otg current regulation v iotg_reg_rng input current regulation differential voltage range v ireg_dpm = v acp ? v acn 0 81.28 mv i otg_acc input current regulation accuracy with 50-ma lsb , with 10- acp/acn series resistor reg0x 09/08() = 0x3c00h 2800 3000 3200 ma reg0x 09/08() = 0x1e00h 1300 1500 1700 ma reg0x 09/08() = 0x0a00h 300 500 700 ma otg voltage regulation v ireg_dpm_rng input voltage regulation range voltage on vbus 4.48 20.8 v v otg_reg_acc otg voltage regulation accuracy reg0x 0b/0a()=0x3cc0h 20.032 v ? 2% 2% reg0x 0b/0a()=0x1d80h 12.032 v ? 2% 2% reg0x 0b/0a()=0x0240h 5.056 v ? 3% 3% reference and buffer regn regulator v regn_reg regn regulator voltage (0 ma ? 60 ma) v vbus = 10 v 5.7 6 6.3 v v dropout regn voltage in drop out mode v vbus = 5 v, i load = 20 ma 3.8 4.3 4.6 v i regn_lim_charging regn current limit when converter is enabled v vbus = 10 v, force v regn = 4 v 50 65 ma c regn regn output capacitor required for stability i load = 100 a to 50 ma 2.2 f c vdda regn output capacitor required for stability i load = 100 a to 50 ma 1 f quiescent current i bat_batfet_on system powered by battery. batfet on. i srn + i srp + i sw2 + i btst2 + i sw1 + i btst1 + acp + i acn + i vbus + i vsys vbat = 18 v, reg0x 01[7] = 1, in low power mode 22 45 a vbat = 18 v, reg0x 01[7] = 0, reg0x 31[6:5] = 01, regn off 105 175 a vbat=18 v, reg0x 01[7] = 0, reg0x 31[6:5] = 10, regn off 60 90 a vbat = 18 v, reg0x 01[7] = 0, reg0x 31[4] = 0, regn on, en_psys 860 1150 a vbat = 18 v, reg0x 01[7] = 0, reg0x = 1, regn on 960 1250 i ac_sw_light_buck input current during pfm in buck mode, no load, i vbus + i acp + i acn + i vsys + i srp + i srn + i sw1 + i btst + i sw2 + i btst2 vin = 20 v, vbat = 12.6 v, 3 s, reg0x 01[2] = 0; mosfet qg = 4 nc 2.2 ma
11 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over t j = ? 40 to 125 c (unless otherwise noted) parameter test conditions min typ max unit i ac_sw_light_boost input current during pfm in boost mode, no load, i vbus + i acp + i acn + i vsys + i srp + i srn + i sw1 + i btst2 + i sw2 + i btst2 vin = 5 v, vbat = 8.4 v, 2 s, reg0x 01[2] = 0; mosfet qg = 4 nc 2.7 ma i ac_sw_light_buckboost input current during pfm in buck boost mode, no load, i vbus + i acp + i acn + i vsys + i srp + i srn + i sw1 + i btst1 + i sw2 + i btst2 vin = 12 v, vbat = 12 v, reg0x 01[2] = 0; mosfet qg = 4 nc 2.4 ma i otg_standby quiescent current during pfm in otg mode i vbus + i acp + i acn + i vsys + i srp + i srn + i sw1 + i btst2 + i sw2 + i btst2 vbat = 8.4 v, vbus = 5 v, 800-khz switching frequency, mosfet qg = 4 nc 3 ma vbat = 8.4 v, vbus = 12 v, 800-khz switching frequency, mosfet qg = 4 nc 4.2 vbat = 8.4 v, vbus = 20 v, 800-khz switching frequency, mosfet qg = 4 nc 6.2 v acp/n_op input common mode range voltage on acp/acn 3.8 26 v v iadpt_clamp i adpt output clamp voltage 3.1 3.2 3.3 v i iadpt i adpt output current 1 ma a iadpt input current sensing gain v (iadpt) / v (acp-acn) , reg0x 00[4] = 0 20 v/v v (iadpt) / v (acp-acn) , reg0x 00[4] = 1 40 v/v v iadpt_acc input current monitor accuracy v (acp-acn) = 40.96 mv ? 2% 2% v (acp-acn) = 20.48 mv ? 3% 3% v (acp-acn) =10.24 mv ? 6% 6% v (acp-acn) = 5.12 mv ? 10% 10% c iadpt_max maximum output load capacitance 100 pf v srp/n_op battery common mode range voltage on srp/srn 2.5 18 v v ibat_clamp ibat output clamp voltage 3.05 3.2 3.3 v i ibat ibat output current 1 ma a ibat charge and discharge current sensing gain on ibat pin v (ibat) / v (srn-srp) , reg0x 00[3] = 0, 8 v/v v (ibat) / v (srn-srp) , reg0x 00[3] = 1, 16 v/v i ibat_chg_acc charge and discharge current monitor accuracy on ibat pin v (srn-srp) = 40.96 mv ? 2% 2% v (srn-srp) = 20.48 mv ? 3% 4% v (srn-srp) =10.24 mv ? 6% 6% v (srn-srp) = 5.12 mv ? 12% 12% c ibat_max maximum output load capacitance 100 pf system power sense amplifier v psys psys output voltage range 0 3.3 v i psys psys output current 0 160 a a psys psys system gain v (psys) / (p (in) + p (bat)) , reg0x 31[1] = 1 1 a/w
12 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over t j = ? 40 to 125 c (unless otherwise noted) parameter test conditions min typ max unit v psys_acc psys gain accuracy (reg0x 31[1] = 1) adapter only with system power = 19.5 v / 45 w, t a = 0 to 85 c ? 5% 5% adapter only with system power = 19.5 v / 45 w, t a = ? 40 to 125 c ? 7% 6% battery only with system power = 11 v / 44 w, t a = 0 to 85 c ? 5% 5% battery only with system power = 11 v / 44 w, t a = ? 40 to 125 c ? 6% 6% v psys_clamp psys clamp voltage 3 3.3 v comparator vbus under voltage lockout comparator v vbus_uvloz vbus undervoltage rising threshold vbus rising 2.34 2.55 2.77 v v vbus_uvlo vbus undervoltage falling threshold vbus falling 2.2 2.4 2.6 v v vbus_uvlo_hyst vbus undervoltage hysteresis 150 mv v vbus_conven vbus converter enable rising threshold vbus rising 3.2 3.5 3.9 v v vbus_convenz vbus converter enable falling threshold vbus falling 2.9 3.2 3.5 v v vbus_conven_hyst vbus converter enable hysteresis 400 mv battery under voltage lockout comparator v vbat_uvloz vbat undervoltage rising threshold vsrn rising 2.35 2.55 2.75 v v vbat_uvlo vbat undervoltage falling threshold vsrn falling 2.2 2.4 2.6 v v vbat_uvlo_hyst vbat undervoltage hysteresis 150 mv v vbat_otgen vbat otg enable rising threshold vsrn rising 3.3 3.55 3.75 v v vbat_otgenz vbat otg enable falling threshold vsrn falling 3 3.2 3.4 v v vbat_otgen_hyst vbat otg enable hysteresis 350 mv vbus under voltage comparator (otg mode) v vbus_otg_uv vbus undervoltage falling threshold as percentage of reg0x 07/06() 85.0% t vbus_otg_uv vbus undervoltage deglitch time 7 ms vbus over voltage comparator (otg mode) v vbus_otg_ov vbus overvoltage rising threshold as percentage of reg0x 07/06() 105% t vbus_otg_ov vbus over-voltage deglitch time 10 ms v bat_sysmin_rise ldo mode to fast charge mode threshold, vsrn rising as percentage of 0x 0d/0c() 98% 100% 102% v bat_sysmin_fall ldo mode to fast charge mode threshold, vsrn falling as percentage of 0x 0d/0c() 97.5%
13 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over t j = ? 40 to 125 c (unless otherwise noted) parameter test conditions min typ max unit v bat_sysmin_hyst fast charge mode to ldo mode threshold hysteresis as percentage of 0x 0d/0c() 2.5% battery lowv comparator (pre-charge to fast charge thresold for 1s) v batlv_fall batlowv falling threshold 1 s 2.80 v v batlv_rise batlowv rising threshold 3.00 v v batlv_rhyst batlowv hysteresis 200 mv input over-voltage comparator (acovp) v acov_rise vbus overvoltage rising threshold vbus rising 25 26 27 v v acov_fall vbus overvoltage falling threshold vbus falling 24 24.5 25 v v acov_hyst vbus overvoltage hysteresis 1.5 v t acov_rise_deg vbus overvoltage rising deglitch vbus rising to stop converter 100 s t acov_fall_deg vbus overvoltage falling deglitch vbus falling to start converter 1 ms input over current comparator (acoc) v acoc acp to acn rising threshold, w.r.t. ilim2 in reg0x 37[7:3] voltage across input sense resistor rising, reg0x 32[2] = 1 195% 210% 225% v acoc_floor measure between acp and acn set idpm to minimum 44 50 56 mv v acoc_ceiling measure between acp and acn set idpm to maximum 172 180 188 mv t acoc_deg_rise rising deglitch time deglitch time to trigger acoc 250 s t acoc_relax relax time relax time before converter starts again 250 ms system over-voltage comparator (sysovp) v sysovp_rise system overvoltage rising threshold to turn off converter 1 s 4.85 5 5.1 v 2 s 11.7 12 12.2 3 s 19 19.5 20 4 s 19 19.5 20 v sysovp_fall system overvoltage falling threshold 1 s 4.8 v 2 s 11.5 3 s 19 4 s 19 i sysovp discharge current when sysovp stop switching was triggered on sys 20 ma bat over-voltage comparator (batovp) v batovp_rise overvoltage rising threshold as percentage of v bat_reg in reg0x 05/04() 1 s, 4.2 v 102.5% 104% 106% 2 s - 4 s 102.5% 104% 105% v batovp_fall overvoltage falling threshold as percentage of vbat_reg in reg0x 05/04() 1 s 100% 102% 104% 2 s - 4 s 100% 102% 103% v batovp_hyst overvoltage hysteresis as percentage of v bat_reg in reg0x 05/04() 1 s 2% 2 s - 4 s 2% i batovp discharge current during batovp on srp and srn 20 ma
14 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over t j = ? 40 to 125 c (unless otherwise noted) parameter test conditions min typ max unit t batovp_rise overvoltage rising deglitch to turn off batdrv to disable charge 20 ms converter over-current comparator (q2) vocp_limit_q2 converter over-current limit reg0x 32[5]=1 150 mv reg0x 32[5]=0 210 vocp_limit_syssh ort_q2 system short or srn < 2.5 v reg0x 32[5]=1 45 mv reg0x 32[5]=0 60 converter over-current comparator (acx) vocp_limit_q3 converter over-current limit reg0x 32[4]=1 150 mv reg0x 32[4]=0 280 vocp_limit_syssh ort_q3 system short or srn < 2.5 v reg0x 32[4]=1 90 mv reg0x 32[4]=0 150 thermal shutdown comparator t shut_rise thermal shutdown rising temperature temperature increasing 155 c t shutf_fall thermal shutdown falling temperature temperature reducing 135 c t shut_hys thermal shutdown hysteresis 20 c t shut_rdeg thermal shutdown rising deglitch 100 s t shut_fhys thermal shutdown falling deglitch 12 ms vsys prochot comparator v sys_ prochot v sys threshold falling threshold reg0x 36[7:6] = 00, 1 s 2.85 v reg0x 36[7:6] = 00, 2 ? 4 s 5.75 v reg0x 36[7:6] = 01, 1 s 2.95 3.1 3.25 v reg0x 36[7:6] = 01, 2 ? 4 s 5.8 5.95 6.1 v reg0x 36[7:6] = 10, 1 s 3.3 v reg0x 36[7:6] = 10, 2 ? 4 s 6.25 v reg0x 36[7:6] = 11, 1 s 3.5 v reg0x 36[7:6] = 11, 2 ? 4 s 6.5 v t sys_pro_rise_deg v sys rising deglitch for throttling 8 s icrit prochot comparator v icrit_pro input current rising threshold for throttling as 10% above ilim2 (reg0x 37[7:3]) reg0x 37[7:3] = 00000 105% 110% 116% reg0x 37[7:3] = 01001 142% 150% 156% inom prochot comparator v inom_pro inom rising threshold as 10% above iin (reg0x 0f/0e()) 105% 110% 116% idchg prochot comparator v idchg_pro idchg threshold for throttling for idschg of 6 a reg0x 39[7:2] =001100 6272 ma 95% 102% independent comparator v indep_cmp independent comparator threshold reg0x30[7] = 1, cmpin falling 1.17 1.2 1.23 v reg0x30[7] = 0, cmpin falling 2.27 2.3 2.33 v
15 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over t j = ? 40 to 125 c (unless otherwise noted) parameter test conditions min typ max unit v indep_cmp_hys independent comparator hysteresis reg0x 06[6] = 0, cmpin falling 100 mv power mosfet driver pwm oscillator and ramp f sw pwm switching frequency reg0x 01[1] = 0 1020 1200 1380 khz reg0x 01[1] = 1 680 800 920 khz batfet gate driver (batdrv) v batdrv_on gate drive voltage on batfet 8.5 10 11.5 v v batdrv_diode drain-source voltage on batfet during ideal diode operation 30 mv r batdrv_on measured by sourcing 10- a current to batdrv 3 4 6 k ? r batdrv_off measured by sinking 10- a current from batdrv 1.2 2.1 k ? pwm high side driver (hidrv q1) r ds_hi_on_q1 high side driver (hsd) turnon resistance v btst1 ? v sw1 = 5 v 6 r ds_hi_off_q1 high side driver turnoff resistance v btst1 ? v sw1 = 5 v 1.3 2.2 v btst1_refresh bootstrap refresh comparator falling threshold voltage v btst1 ? v sw1 when low side refresh pulse is requested 3.2 3.7 4.6 v pwm high side driver (hidrv q4) r ds_hi_on_q4 high side driver (hsd) turnon resistance v btst2 ? v sw2 = 5 v 6 r ds_hi_off_q4 high side driver turnoff resistance v btst2 ? v sw2 = 5 v 1.5 2.4 v btst2_refresh bootstrap refresh comparator falling threshold voltage v btst2 ? v sw2 when low side refresh pulse is requested 3.3 3.7 4.6 v pwm low side driver (lodrv q2) r ds_lo_on_q2 low side driver (lsd) turnon resistance v btst1 ? v sw1 = 5.5 v 6 r ds_lo_off_q2 low side driver turnoff resistance v btst1 ? v sw1 = 5.5 v 1.7 2.6 pwm low side driver (lodrv q3) r ds_lo_on_q3 low side driver (lsd) turnon resistance v btst2 ? v sw2 = 5.5 v 7.6 r ds_lo_off_q3 low side driver turnoff resistance v btst2 ? v sw2 = 5.5 v 2.9 4.6 internal soft start during charge enable ssstep_dac soft start step size 64 ma ssstep_dac soft start step time 8 s integrated btst diode (d1) v f_d1 forward bias voltage i f = 20 ma at 25 c 0.8 v v r_d1 reverse breakdown voltage i r = 2 a at 25 c 20 v integrated btst diode (d2) v f_d2 forward bias voltage i f = 20 ma at 25 c 0.8 v v r_d2 reverse breakdown voltage i r = 2 a at 25 c 20 v pwm drivers timing
16 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over t j = ? 40 to 125 c (unless otherwise noted) parameter test conditions min typ max unit interface logic input (sda, scl, en_otg) v in_ lo input low threshold i2c 0.4 v v in_ hi input high threshold i2c 1.3 v logic output open drain (sda, chrg_ok, cmpout) v out_ lo output saturation voltage 5-ma drain current 0.4 v v out_ leak leakage current v = 7 v ? 1 1 ma logic output open drain sda v out_ lo_sda output saturation voltage 5 ma drain current 0.4 v v out_ leak_sda leakage current v = 7v ? 1 1 ma logic output open drain chrg_ok v out_ lo_chrg_ok output saturation voltage 5 ma drain current 0.4 v v out_ leak _chrg_ok leakage current v = 7v ? 1 1 ma logic output open drain cmpout v out_ lo_cmpout output saturation voltage 5 ma drain current 0.4 v v out_ leak _cmpout leakage current v = 7v ? 1 1 ma logic output open drain ( prochot) v out_ lo_prochot output saturation voltage 50- pullup to 1.05 v / 5-ma load 300 mv v out_ leak_prochot leakage current v = 5.5 v ? 1 1 ma analog input (ilim_hiz) v hiz_ lo voltage to get out of hiz mode ilim_hiz pin rising 0.8 v v hiz_ high voltage to enable hiz mode ilim_hiz pin falling 0.4 v analog input (cell_batpresz) v cell_4s 4s regn = 6 v, as percentage of regn 68.4% 75% v cell_3s 3s regn = 6 v, as percentage of regn 51.7% 55% 65% v cell_2s 2s regn = 6 v, as percentage of regn 35% 40% 49.1% v cell_1s 1s regn = 6 v, as percentage of regn 18.4% 25% 31.6% v cell_batpresz_rise battery is present 18% v cell_batpresz_fall battery is removed cell_batpresz falling 15% analog input (comp1, comp2) i leak_comp1 comp1 leakage ? 120 120 na i leak_comp2 comp2 leakage ? 120 120 na 7.6 timing requirements min typ max unit i2c timing characteristics t r sclk/sdata rise time 1 s t f sclk/sdata fall time 300 ns t w(h) sclk pulse width high 4 50 s t w(l) sclk pulse width low 4.7 s t su(sta) setup time for start condition 4.7 s t h(sta) start condition hold time after which first clock pulse is generated 4 s
17 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated timing requirements (continued) min typ max unit (1) user can adjust threshold via smbus chargeoption() reg0x 01/00. t su(dat) data setup time 250 ns t h(dta) data hold time 300 ns t su(stop) setup time for stop condition 4 s t (buf) bus free time between start and stop condition 4.7 s f s(cl) clock frequency 100 400 khz host communication failure t boot deglitch for watchdog reset signal 10 ms t wdi watchdog timeout period, chargeoption() bit [6:5] = 01 (1) 35 44 53 s watchdog timeout period, chargeoption() bit bit [6:5] = 10 (1) 70 88 105 s watchdog timeout period, chargeoption() bit bit [6:5] = 11 (1) (default) 140 175 210 s 7.7 typical characteristics vin = 5 v figure 1. light load efficiency vin = 12 v figure 2. light load efficiency vin = 20 v figure 3. light load efficiency vin = 5 v figure 4. system efficiency output current (a) efficiency (%) 0 0.01 0.02 0.03 0.04 0.05 60 65 70 75 80 85 90 d001 vout = 6.1 v vout = 8.4 v vout = 9.2 v vout = 12.5 v output current (a) efficiency (%) 0 0.01 0.02 0.03 0.04 0.05 60 65 70 75 80 85 90 d001 vout = 6.1 v vout = 8.4 v vout = 9.2 v vout = 12.5 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 d001 vout = 3.7 v vout = 7.4 v vout = 11.1 v vout = 14.8 v output current (a) efficiency (%) 0 0.01 0.02 0.03 0.04 0.05 60 65 70 75 80 85 90 d001 vout = 6.1 v vout = 8.4 v vout = 9.2 v vout = 12.5 v
18 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) vin = 9 v figure 5. system efficiency vin = 12 v figure 6. system efficiency vin = 20 v figure 7. system efficiency figure 8. otg efficiency with 1s battery figure 9. otg efficiency with 2s battery figure 10. otg efficiency with 3s battery output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 d001 votg = 5 v votg = 12 v votg = 20 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 98 d001 votg = 5 v votg = 12 v votg = 20 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 98 d001 vout = 3.7 v vout = 7.4 v vout = 11.1 v vout = 14.8 v output current (a) efficiency (%) 0 1 2 3 4 5 80 82 84 86 88 90 92 94 96 d001 votg = 5 v votg = 12 v votg = 20 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 98 d001 vout = 3.7 v vout = 7.4 v vout = 11.1 v vout = 14.8 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 98 d001 vout = 3.7 v vout = 7.4 v vout = 11.1 v vout = 14.8 v
19 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) figure 11. otg efficiency with 4s battery output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 98 d001 votg = 5 v votg = 12 v votg = 20 v
20 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8 detailed description 8.1 overview the BQ25703A is a buck boost nvdc (narrow voltage dc) charge controller for multi-chemistry portable applications such as notebook, detachable, ultrabook, tablet and other mobile devices with rechargeable batteries. it provides seamless transition between converter operation modes (buck, boost, or buck boost), fast transient response, and high light load efficiency. the BQ25703A supports wide range of power sources, including usb pd ports, legacy usb ports, traditional ac- dc adapters, etc. it takes input voltage from 3.5 v to 24 v, and charges battery of 1-4 series. it also supports usb on-the-go (otg) to provide 4.48v to 20.8v output at usb port. the BQ25703A features dynamic power management (dpm) to limit the input power and avoid ac adapter overloading. during battery charging, as the system power increases, the charging current will reduce to maintain total input current below adapter rating. if system power demand temporarily exceeds adapter rating, the BQ25703A supports nvdc architecture to allow battery discharge energy to supplement system power. for details, refer to system voltage regulation section. in order to be compliant with intel imvp8 compliant system, the BQ25703A includes psys function to monitor the total platform power from adapter and battery. besides psys, it provides both an independent input current buffer (iadpt) and a battery current buffer (ibat) with highly accurate current sense amplifiers. if the platform power exceeds the available power from adapter and battery, a prochot signal is asserted to cpu so that the cpu optimizes its performance to the power available to the system. the i2c controls input current, charge current and charge voltage registers with high resolution, high accuracy regulation limits. it also sets the prochot timing and threshold profile to meet system requirements.
21 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2 functional block diagram 50ms rising deglitch 20x** 20x** regn ldo smbus/i2c interface chargeoption0() chargeoption1() chargeoption2() chargecurrent() chargevoltage() inputcurrent() inputvoltage() minsysvoltage() otgvoltage() otgcurrent() 3.9v acovp 26v chrg_ok_drv vref_idpm, or vref_iotg en_hiz pwm en_regn vbus chrg_ok acp acn iadpt srp srn sda scl pgnd lodrv1 regn sw1 hidrv1 btst1 vref_vbat BQ25703A block diagram ** programmable in register 4 2 3 pwm driver logic ibat psys cell_batpresz processor hot prochot iadpt ibat vsys acn (acp-acn) srn (srn-srp) 16x vref_ichg ilim_hiz lodrv2 sw2 hidrv2 btst2 cmpin cmpout vref_cmp** cmp_deg** loop selector and error amplifier vref_vdpm or vref_votg vref_ilim vsns_idpm, or vsns_iotg vsns_ichg vsns_vbat vsys vsns_vsys vref_vsys vsns_vdpm or vsys_votg over current over voltage detect vsns_vsys vsns_vbat vsns_ichg vsns_idchg vsns_idpm vsns_vdpm vsns_idchg loop regulation reference vref_vsys vref_vbat vref_ichg vref_idpm vref_vdpm en_learn en_ldo en_chrg en_hiz en_learn en_ldo en_chrg batdrv vsys vsys-10v ldo mode gate control batpresz chrg_ok decoder cell_config comp1 comp2 decoder en_hiz en_otg en_otg en_otg vdda 8 9 10 vsns_ichg vref_iotg vref_votg 1 6 20 19 22 12 13 5 11 18 26 23 27 24 25 29 28 7 32 31 30 21 17 16 15 14 copyright ? 2017, texas instruments incorporated en_regn 50ms rising deglitch
22 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3 feature description 8.3.1 power-up from battery without dc source if only battery is present and the voltage is above v vbat_uvloz , the batfet turns on and connects battery to system. by default, the charger is in low power mode (reg 0x01[7] = 1) with lowest quiescent current. the ldo stays off. when device moves to performance mode (reg 0x01[7] = 0), the host enables ibat buffer through i2c to monitor discharge current. for psys, prochot or independent comparator, regn ldo is enabled for an accurate reference. 8.3.2 power-up from dc source when an input source plugs in, the charger checks the input source voltage to turn on ldo and all the bias circuits. it sets the input current limit before the converter starts. the power-up sequence from dc source is as follows: 1. 50 ms after vbus above v vbus_conven , enable 6 v ldo and chrg_ok goes high 2. input voltage and current limit setup 3. battery cell configuration 4. 150 ms after vbus above v vbus_conven , converter powers up. 8.3.2.1 chrg_ok indicator chrg_ok is an active high open drain indicator. it indicates the charger is in normal operation when the following conditions are valid: ? vbus is above v vbus_conven ? vbus is below v acov ? no mosfet/inductor fault 8.3.2.2 input voltage and current limit setup after chrg_ok goes high, the charger sets default input current limit in reg 0x0f/0e() to 3.30 a. the actual input current limit is the lower setting of reg 0x0f/0e() and ilim_hiz pin. charger initiates a vbus voltage measurement without load (vbus at noload). the default vindpm threshold is vbus at noload ? 1.28 v. after input current and voltage limits are set, the charger device is ready to power up. the host can always update input current and voltage limit based on input source type. 8.3.2.3 battery cell configuration cell_batpresz pin is biased with resistors from regn to cell_batpresz to gnd. after vdda ldo is activated, the device detects the battery configuration through cell_batpresz pin bias voltage. refer to electrical characteristics for cell setting thresholds. table 1. battery cell configuration cell count pin voltage w.r.t. vdda battery voltage (reg0x 05/04) sysovp 4s 75% 16.800v no sysovp (refer to system overvoltage protection (sysovp) section) 3s 55% 12.592v 18.5v 2s 40% 8.400v 12v 1s 25% 4.192v 5v 8.3.2.4 device hi-z state the charger enters hi-z mode when ilim_hiz pin voltage is below 0.4 v or reg0x 35[7] is set to 1. during hi-z mode, the input source is present, and the charger is in the low quiescent current mode with regn ldo enabled.
23 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.3 usb on-the-go (otg) the device supports usb otg operation to deliver power from the battery to other portable devices through usb port. the otg mode output voltage is set in reg0x 07/06(). the otg mode output current is set in reg0x 09/08(). the otg operation can be enabled if the conditions are valid: ? valid battery voltage is set reg0x 05/04() ? otg output voltage is set in reg0x 07/06() and output current is set in reg0x 09/08() ? en_otg pin is high and reg0x 35[4] = 1 ? vbus is below v vbus_uvlo ? 10 ms after the above conditions are valid, converter starts and vbus ramps up to target voltage. chrg_ok pin goes high if reg0x01[3] = 1. 8.3.4 converter operation the charger employs a synchronous buck-boost converter that allows charging from a standard 5-v or a high- voltage power source. the charger operates in buck, buck-boost and boost mode. the buck-boost can operate uninterruptedly and continuously across the three operation modes. table 2. mosfet operation mode buck buck-boost boost q1 switching switching on q2 switching switching off q3 off switching switching q4 on switching switching 8.3.4.1 inductor setting through iadpt pin the charger reads the inductor value through the iadpt pin. table 3. inductor setting on iadpt pin inductor in use resistor on iadpt pin 1 h 93 k 2.2 h 137 k 3.3 h 169 k 8.3.4.2 continuous conduction mode (ccm) with sufficient charge current, the inductor current does not cross 0, which is defined as ccm. the controller starts a new cycle with ramp coming up from 200 mv. as long as error amplifier output voltage is above the ramp voltage, the high-side mosfet (hsfet) stays on. when the ramp voltage exceeds error amplifier output voltage, hsfet turns off and lowside mosfet (lsfet) turns on. at the end of the cycle, ramp gets reset and lsfet turns off, ready for the next cycle. there is always break-before-make logic during transition to prevent cross-conduction and shoot-through. during the dead time when both mosfets are off, the body-diode of the low-side power mosfet conducts the inductor current. during ccm, the inductor current always flows and creates a fixed two-pole system. having the lsfet turn-on keeps the power dissipation low and allows safe charging at high currents. 8.3.4.3 pulse frequency modulation (pfm) in order to improve converter light-load efficiency, the BQ25703A switches to pfm control at light load when inductor current is less than 500 ma. the effective switching frequency will decrease accordingly when system load decreases. the minimum frequency can be limit to 25 khz (chargeoption0() bit[10]=1). to have higher light load efficiency, set en_ooa bit low (chargeoption0() bit[10] = 0).
24 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.5 current and power monitor 8.3.5.1 high-accuracy current sense amplifier (iadpt and ibat) as an industry standard, a high-accuracy current sense amplifier (csa) is used to monitor the input current during forward charging, or output current during otg (iadpt) and the charge/discharge current (ibat). iadpt voltage is 20 or 40 the differential voltage across acp and acn. ibat voltage is 8x/16 (during charging), or 8 /16 (during discharging) of the differential across srp and srn. after input voltage or battery voltage is above uvlo, iadpt output becomes valid. to lower the voltage on current monitoring, a resistor divider from csa output to gnd can be used and accuracy over temperature can still be achieved. ? v (iadpt) = 20 or 40 (v (acp) ? v (acn) ) during forward mode, or 20 or 40 (v (acn) ? v (acp) ) during reverse otg mode. ? v (ibat) = 8 or 16 (v (srp) ? v (srn) ) during forward mode. ? v (ibat) = 8 or 16 (v (srn) ? v (srp) ) during forward mode, or reverse otg mode. a maximum 100-pf capacitor is recommended to connect on the output for decoupling high-frequency noise. an additional rc filter is optional, if additional filtering is desired. note that adding filtering also adds additional response delay. the csa output voltage is clamped at 3.3 v. 8.3.5.2 high-accuracy power sense amplifier (psys) the charger monitors total system power. during forward mode, the input adapter powers system. during reverse otg mode, the battery powers the system and vbus output. the ratio of psys current and total power k psys can be programmed in reg0x 31[1] with default 1 a/w. the input and charge sense resistors (rac and rsr) are programmed in reg0x 31[3:2]. psys voltage can be calculated with equation 1 where iin > 0 when adapter is in forward charging, and ibat > 0 when the battery is in discharge when the battery is in discharge. (1) for proper psys functionality, rac and rsr values are limited to 10 m and 20 m . 8.3.6 input source dynamic power manage refer to input current and input voltage registers for dynamic power management . 8.3.7 two-level adapter current limit (peak power mode) usually adapter can supply current higher than dc rating for a few milliseconds to tens of milliseconds. the charger employs two-level input current limit, or peak power mode, to fully utilize the overloading capability and minimize battery discharge during cpu turbo mode. peak power mode is enabled in reg0x 33[5]. the dc current limit, or i lim1 , is the same as adapter dc current, set in reg 0x0f/0e(). the overloading current, or i lim2 , is set in reg0x 37[7:3], as in percentage of i lim1. when the charger detects input current surge and battery discharge due to load transient, it applies i lim2 for t ovld in reg0x 33[7:6], first, and then i lim1 for up to t max ? t ovld time. t max is programmed in reg0x 33[1:0]. after t max, if the load is still high, another peak power cycle starts. charging is disabled during t max, ; once t max, expires, charging continues. psys psys psys acp in bat bat v r k (v i v i ) u u u
25 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 12. two-level adapter current limit timing diagram 8.3.8 processor hot indication when cpu is running turbo mode, the system peak power may exceed available power from adapter and battery together. the adapter current and battery discharge peak current, or system voltage drop is indications that system power are too high. the charger processor hot function monitors these events, and prochot pulse is asserted. once cpu receives prochot pulse from charger, it slows down to reduce system power. the processor hot function monitors these events, and prochot pulse is asserted. the prochot triggering events include: ? icrit: adapter peak current, as 110% of i lim2 ? inom: adapter average current (110% of input current limit) ? idchg: battery discharge current ? vsys: system voltage on vsys ? adapter removal: upon adapter removal (chrg_ok pin high to low) ? battery removal: upon battery removal (cell_batpresz pin goes low) ? cmpout: independent comparator output (cmpout pin high to low) the threshold of icrit, idchg or vsys, and the deglitch time of icrit, inom, idchg or cmpout are programmable through i2c. each triggering event can be individually enabled in reg0x 38[6:0]. when any event in prochot profile is triggered, prochot is asserted low for minimum 10 ms programmable in 0x 36[4:3]. at the end of the 10 ms, if the prochot event is still active, the pulse gets extended. t ovld t max t ovld ivbus prochot i lim1 i lim2 i crit isys ibat battery discharge
26 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated figure 13. prochot profile 8.3.8.1 prochot during low power mode during low power mode (reg0x 01[7] = 1), the charger offers a low quiescent current (~150 a) low power prochot function uses the independent comparator to monitor battery discharge current and system voltage, and assert prochot to cpu. below lists the register setting to enable prochot during low power mode. ? reg 0x01[7] = 1 ? reg0x 38[5:0] = 000000 ? reg0x30[6:4] = 100 ? independent comparator threshold is always 1.2 v ? when reg0x 31[6] = 1, charger monitors discharge current. connect cmpin to voltage proportional to ibat pin. prochot triggers from high to low when cmpin voltage falls below 1.2 v. ? when reg0x 31[5] = 1, charger monitors system voltage. connect cmpin to voltage proportional to system. prochot triggers from high to low when cmpin voltage rises above 1.2 v. iadp idchg ref_dchg ref cmpout 20 s deglitch 10 ms debounce vsrp inom adjustable deglitch prochot icrit cell_batpresz (one shot on pin falling edge) 10 ms 1.05v <0.3v 50 chrg_ok (one shot on pin falling edge) copyright ? 2017, texas instruments incorporated
27 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 14. prochot low power mode implementation 8.3.8.2 prochot status reg0x 22[6:0] reports which event in the profile triggers prochot by setting the corresponding bit to 1. the status bit can be reset back to 0 after it is read by host, and current prochot event is no longer active. assume there are two prochot events, event a and event b. event a triggers prochot first, but event b is also active. both status bits will be high. at the end of the 10 ms prochot pulse, if prochot is still active (either by a or b), the prochot pulse is extended. 8.3.9 device protection 8.3.9.1 watchdog timer the charger includes watchdog timer to terminate charging if the charger does not receive a write maxchargevoltage() or write chargecurrent() command within 175 s (adjustable via reg0x 01[6:5]). when watchdog timeout occurs, all register values are kept unchanged except chargecurrent() resets to zero. battery charging is suspended. write maxchargevoltage() or write chargecurrent() commands must be re-sent to reset watchdog timer and resume charging. writing reg0x 01[6:5] = 00 to disable watchdog timer also resumes charging. 8.3.9.2 input overvoltage protection (acov) the charger has fixed acov voltage. when vbus pin voltage is higher than acov, it is considered as adapter over voltage. chrg_ok will be pulled low, and converter will be disabled. as system falls below battery voltage, batfet will be turned on. when vbus pin voltage falls below acov, it is considered as adapter voltage returns back to normal voltage. chrg_ok is pulled high by external pull up resistor. the converter resumes if enable conditions are valid. 8.3.9.3 input overcurrent protection (acoc) if the input current exceeds the 1.25 or 2 (reg0x 32[2]) of i lim2 _vth (reg0x 37[7:3]) set point, converter stops switching. after 300 ms, converter starts switching again. prochot independent comparator 1.2 v bq2570x cmpin v sys v voltage ( v srn v srp ) v voltage copyright ? 2017, texas instruments incorporated
28 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.9.4 system overvoltage protection (sysovp) when the converter starts up, the bq25700 reads cell pin configuration and sets maxchargevoltage() and sysovp threshold (1s ? 5 v, 2s ? 12 v, 3s ? 18.5 v). before regx 05/04() is written by the host, the battery configuration will change with cell pin voltage. when sysovp happens, the device latches off the converter. reg20[4] is set as 1. the user can clear latch-off by either writing 0 to the sysovp bit or removing and plugging in the adapter again. after latch-off is cleared, the converter starts again. 8.3.9.5 battery overvoltage protection (batovp) battery over-voltage may happen when battery is removed during charging or the user plugs in a wrong battery. the batovp threshold is 104% (1 s) or 102% (2 s to 4 s) of regulation voltage set in reg0x 05/04(). 8.3.9.6 battery short if bat voltage falls below sysmin during charging, the maximum current is limited to 384 ma. 8.3.9.7 thermal shutdown (tshut) the wqfn package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junction temperatures low. as added level of protection, the charger converter turns off for self- protection whenever the junction temperature exceeds the 155 c. the charger stays off until the junction temperature falls below 135 c. during thermal shut down, the ldo current limit is reduced to 16 ma and regn ldo stays off. when the temperature falls below 135 c, charge can be resumed with soft start. 8.4 device functional modes 8.4.1 forward mode when input source is connected to vbus, BQ25703A is in forward mode to regulate system and charge battery. 8.4.1.1 system voltage regulation with narrow vdc architecture the BQ25703A employs narrow vdc architecture (nvdc) with batfet separating system from battery. the minimum system voltage is set by minsystemvoltage(). even with a deeply depleted battery, the system is regulated above the minimum system voltage. when the battery is below minimum system voltage setting, the batfet operates in linear mode (ldo mode). as the battery voltage rises above the minimum system voltage, batfet is fully on when charging or in supplement mode and the voltage difference between the system and battery is the vds of batfet. system voltage is regulated 160 mv above battery voltage when batfet is off (no charging or no supplement current). see system voltage regulation for details on system voltage regulation and register programming. 8.4.1.2 battery charging the BQ25703A charges 1-4 cell battery in constant current (cc), and constant voltage (cv) mode. based on cell_batprez pin setting, the charger sets default battery voltage 4.2v/cell to chargevoltage(), or reg 0x05/04(). according to battery capacity, the host programs appropriate charge current to chargecurrent(), or 0x03/02(). when battery is full or battery is not in good condition to charge, host terminates charge by setting 0x 00[0] to 1, or setting chargecurrent() to zero. see feature description for details on register programming. 8.4.2 usb on-the-go the BQ25703A supports usb otg functionality to deliver power from the battery to other portable devices through usb port (reverse mode). the otg output voltage is compliant with usb pd specification, including 5 v, 9 v, 15 v, and 20 v (reg 0x07/06()). the output current regulation is compliant with usb type c specification, including 500 ma, 1.5 a, 3 a and 5 a (reg 0x09/08()). similar to forward operation, the device switches from pwm operation to pfm operation at light load to improve efficiency.
29 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5 programming the charger supports battery-charger commands that use either write-word or read-word protocols, as summarized in . the smbus address is 12h (0001001_x), where x is the read/write bit. the manufacturerid and deviceid registers are assigned identify the charger device. the manufacturerid register command always returns 40h. 8.5.1 i 2 c serial interface the BQ25703A uses i2c compatible interface for flexible charging parameter programming and instantaneous device status reporting. i 2 c is a bi-directional 2-wire serial interface. only two bus lines are required: a serial data line (sda) and a serial clock line (scl). devices can be considered as masters or slaves when performing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. at that time, any device addressed is considered a slave. the device operates as a slave device with address d6h, receiving control inputs from the master device like micro controller or a digital signal processor through reg00-reg0f. the i 2 c interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits). connecting to the positive supply voltage via a current source or pull-up resistor. when the bus is free, both lines are high. the sda and scl pins are open drain. 8.5.1.1 data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low. one clock pulse is generated for each data bit transferred. figure 15. bit transfer on the i 2 c bus 8.5.1.2 start and stop conditions all transactions begin with a start (s) and can be terminated by a stop (p). a high to low transition on the sda line while scl is high defines a start condition. a low to high transition on the sda line when the scl is high defines a stop condition. start and stop conditions are always generated by the master. the bus is considered busy after the start condition, and free after the stop condition. figure 16. start and stop conditions start (s) stop (p) sda scl sda scl sda scl data line stable; data valid change of data allowed
30 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated programming (continued) 8.5.1.3 byte format every byte on the sda line must be 8 bits long. the number of bytes to be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most significant bit (msb) first. if a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line scl low to force the master into a wait state (clock stretching). data transfer then continues when the slave is ready for another byte of data and release the clock line scl. figure 17. data transfer on the i 2 c bus 8.5.1.4 acknowledge (ack) and not acknowledge (nack) the acknowledge takes place after every byte. the acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. all clock pulses, including the acknowledge 9th clock pulse, are generated by the master. the transmitter releases the sda line during the acknowledge clock pulse so the receiver can pull the sda line low and it remains stable low during the high period of this clock pulse. when sda remains high during the 9th clock pulse, this is the not acknowledge signal. the master can then generate either a stop to abort the transfer or a repeated start to start a new transfer. scl sda start or repeated start s or sr 1 2 7 8 9 msb ack acknowledgement signal from slave 1 2 8 9 ack acknowledgement signal from receiver stop or repeated start p or sr
31 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated programming (continued) 8.5.1.5 slave address and data direction bit after the start, a slave address is sent. this address is 7 bits long followed by the eighth bit as a data direction bit (bit r/w). a zero indicates a transmission (write) and a one indicates a request for data (read). figure 18. complete data transfer 8.5.1.6 single read and write figure 19. single write figure 20. single read if the register address is not defined, the charger ic send back nack and go back to the idle state. 8.5.1.7 multi-read and multi-write the charger device supports multi-read and multi-write. figure 21. multi write scl sda start s 1-7 8 9 ack 1-7 8 9 ack 1-7 8 9 stop p address r/w data ack data
32 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated programming (continued) figure 22. multi read 8.5.1.8 write 2-byte i2c commands a few i2c commands combine two 8-bit registers together to form a complete value. these commands include: ? chargecurrent() ? maxchargevoltage() ? iin_dpm() ? otgvoltage() ? inputvoltage() host has to write lsb command followed by msb command. no other command can be inserted in between these two writes. the charger waits for the complete write to the two registers to decide whether to accept or ignore the new value. after the completion of lsb and msb bytes, the two bytes will be updated at the same time. if host writes msb byte first, the command will be ignored. if the time between write of lsb and msb bytes exceeds watchdog timer, both the lsb and msb commands will be ignored. 8.6 register map table 4. charger command summary i2c addr (msb/lsb) register name type description links 01/00 chargeoption0() r/w charge option 0 go 03/02 chargecurrent() r/w 7-bit charge current setting lsb 64 ma, range 8128 ma go 05/04 maxchargevoltage() r/w 11-bit charge voltage setting lsb 16 mv, default: 1s-4192mv, 2s-8400mv, 3s-12592mv, 4s-16800mv go 31/30 chargeoption1() r/w charge option 1 go 33/32 chargeoption2() r/w charge option 2 go 35/34 chargeoption3() r/w charge option 3 go 37/36 prochotoption0() r/w prochot option 0 go 39/38 prochotoption1() r/w prochot option 1 go 3b/3a adcoption() r/w adc option go 21/20 chargerstatus() r charger status go 23/22 prochotstatus() r prochot status go 25/24 iin_dpm() r 7-bit input current limit in use lsb: 50 ma, range: 50 ma - 6400 ma go 27/26 adcvbus/psys() r 8-bit digital output of input voltage, 8-bit digital output of system power psys: full range: 3.06 v, lsb: 12 mv vbus: full range: 3.2 v - 19.52 v, lsb 64 mv go
33 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated register map (continued) table 4. charger command summary (continued) i2c addr (msb/lsb) register name type description links 29/28 adcibat() r 8-bit digital output of battery charge current, 8-bit digital output of battery discharge current ichg: full range 8.128 a, lsb 64 ma idchg: full range: 32.512 a, lsb: 256 ma go 2b/2a adciincmpin() r 8-bit digital output of input current, 8-bit digital output of cmpin voltage por state - iin: full range: 12.75 a, lsb 50 ma cmpin: full range 3.06 v, lsb: 12 mv go 2d/2c adcvsysvbat() r 8-bit digital output of system voltage, 8-bit digital output of battery voltage vsys: full range: 2.88 v - 19.2 v, lsb: 64 mv vbat: full range : 2.88 v - 19.2 v, lsb 64 mv go 07/06 otgvoltage() r/w 8-bit otg voltage setting lsb 64 mv, range: 4480 ? 20800 mv go 09/08 otgcurrent() r/w 7-bit otg output current setting lsb 50 ma, range: 0 a ? 6350 ma go 0b/0a inputvoltage() r/w 8-bit input voltage setting lsb 64 mv, range: 3200 mv ? 19520 mv go 0d/0c minsystemvoltage() r/w 6-bit minimum system voltage setting lsb: 256 mv, range: 1024 mv - 16182 mv default: 1s-3.584v, 2s-6.144v, 3s-9.216v, 4s- 12.288v go 0f/0e iin_host() r/w 6-bit input current limit set by host lsb: 50-ma, range: 0 ma - 6350 ma go 2e manufacturerid() r manufacturer id - 0x0040h go 2f deviceaddress() r device address id go
34 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.1 setting charge and prochot options 8.6.1.1 chargeoption0 register ( i2c address = 01/00h) [reset = e20eh] figure 23. chargeoption0 register ( i2c address = 01h/00h) [reset = e20eh] 15 14 13 12 11 10 9 8 en_lwpwr wdtmr_adj idpm_auto_ disable otg_on_ chrgok en_ooa pwm_freq reserved r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 reserved en_learn iadpt_gain ibat_gain en_ldo en_idpm chrg_inhibit r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 5. chargeoption0 register (i2c address = 01h) field descriptions i2c 01h field type reset description 7 en_lwpwr r/w 1b low power mode enable 0b: disable low power mode. device in performance mode with battery only. the prochot, current/power monitor buffer and comparator follow register setting. 1b: enable low power mode. device in low power mode with battery only for lowest quiescent current. prochot, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. adc is not available in low power mode.independent comparator can be enabled by setting either reg0x31()[6] or [5] to 1. < default at por > 6-5 wdtmr_adj r/w 11b watchdog timer adjust set maximum delay between consecutive i2c write of charge voltage or charge current command. if device does not receive a write on the reg0x05/04() or the reg0x03/02() within the watchdog time period, the charger will be suspended by setting the reg0x03/02() to 0 ma. after expiration, the timer will resume upon the write of reg0x03/02(), reg0x05/04() or reg0x01[6:5]. the charger will resume if the values are valid. 00b: disable watchdog timer 01b: enabled, 5 sec 10b: enabled, 88 sec 11b: enable watchdog timer, 175 sec < default at por > 4 idpm_auto_ disable r/w 0b idpm auto disable when cell_batpresz pin is low, the charger automatically disables the idpm function by setting en_idpm (reg0x00[1]) to 0. the host can enable idpm function later by writing en_idpm bit (reg0x00[1]) to 1. 0b: disable this function. idpm is not disabled when cell_batpresz goes low. < default at por > 1b: enable this function. idpm is disabled when cell_batpresz goes low. 3 otg_on_ chrgok r/w 0b add otg to chrg_ok drive chrg_ok to high when the device is in otg mode. 0b: disable < default at por > 1b: enable 2 en_ooa r/w 0b out-of-audio enable 0b: no limit of pfm burst frequency < default at por > 1b: set minimum pfm burst frequency to above 25 khz to avoid audio noise
35 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated table 5. chargeoption0 register (i2c address = 01h) field descriptions (continued) i2c 01h field type reset description 1 pwm_freq r/w 1b switching frequency two converter switching frequencies. one for small inductor and the other for big inductor. recommend 800 khz with 2.2 h or 3.3 h, and 1.2 mhz with 1 h or 1.5 h. host has to set the right pwm frequency after device por. 0b: 1200 khz 1b: 800 khz 0 reserved r/w 0b reserved table 6. chargeoption0 register (i2c address = 00h) field descriptions i2c 00h field type reset description 7-6 reserved r/w 00b reserved 5 en_learn r/w 0b learn function allows the battery to discharge while the adapter is present. it calibrates the battery gas gauge over a complete discharge/charge cycle. when the battery voltage is below battery depletion threshold, the system switches back to adapter input by the host. when cell_batpresz pin is low, the device exits learn mode and this bit is set back to 0. 0b: disable learn mode < default at por > 1b: enable learn mode 4 iadpt_gain r/w 0b iadpt amplifier ratio the ratio of voltage on iadpt and voltage across acp and acn. 0b: 20 < default at por > 1b: 40 3 ibat_gain r/w 1b ibat amplifier ratio 0b: 8 1b: 16 < default at por > 2 en_ldo r/w 1b ldo mode enable when battery voltage is below minimum system voltage (reg0x 0d/0c()), the charger is in pre-charge with ldo mode enabled. 0b: disable ldo mode, batfet fully on. precharge current is set by battery pack ldo. the system is regulated by the maxchargevoltage register. 1b: enable ldo mode, precharge current is set by the chargecurrent register and clamped below 384 ma (2 cell ? 4 cell) or 2a (1 cell). the system is regulated by the minsystemvoltage register. < default at por > 1 en_idpm r/w 1b idpm enable host writes this bit to enable idpm regulation loop. when the idpm is disabled by the charger (refer to idpm_auto_disable), this bit goes low. 0b: idpm disabled 1b: idpm enabled < default at por > 0 chrg_inhibit r/w 0b charge inhibit when this bit is 0, battery charging will start with valid values in the maxchargevoltage register and the chargecurrent register. 0b: enable charge < default at por > 1b: inhibit charge
36 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.1.2 chargeoption1 register ( i2c address = 31h/30h) [reset = 211h] figure 24. chargeoption1 register ( i2c address = 31h/30h) [reset = 211h] 15 14 13 12 11 10 9 8 en_ibat en_prochot_lpwr en_psys rsns_rac rsns_rsr psys_ratio reserved r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 cmp_ref cmp_pol cmp_deg force_ latchoff reserved en_ship_ dchg auto_ wakeup_en r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 7. chargeoption1 register (i2c address = 31h) field descriptions i2c 31h field type reset description 7 en_ibat r/w 0b ibat enable enable the ibat output buffer. in low power mode (reg0x01[7] = 1), ibat buffer is always disabled regardless of this bit value. 0b turn off ibat buffer to minimize iq < default at por > 1b: turn on ibat buffer 6-5 en_prochot _lpwr r/w 00b enable prochot during battery only low power mode with battery only, enable idchg or vsys in prochot with low power consumption. do not enable this function with adapter present. refer to prochot during low power mode for more details. 00b: disable low power prochot < default at por > 01b: enable idchg low power prochot 10b: enable vsys low power prochot 11b: reserved 4 en_psys r/w 0b psys enable enable psys sensing circuit and output buffer (whole psys circuit). in low power mode (reg0x01[7] = 1), psys sensing and buffer are always disabled regardless of this bit value. 0b: turn off psys buffer to minimize iq < default at por > 1b: turn on psys buffer 3 rsns_rac r/w 0b input sense resistor rac 0b: 10 m < default at por > 1b: 20 m 2 rsns_rsr r/w 0b charge sense resistor rsr 0b: 10 m < default at por > 1b: 20 m 1 psys_ratio r/w 1b psys gain ratio of psys output current vs total input and battery power with 10-m sense resistor. 0b: 0.25 a/w 1b: 1 a/w < default at por > 0 reserved r/w 0b reserved table 8. chargeoption1 register (i2c address = 30h) field descriptions i2c 30h field type reset description 7 cmp_ref r/w 0b independent comparator reference independent comparator internal reference. 0b: 2.4 v < default at por > 1b: 1.3 v
37 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated table 8. chargeoption1 register (i2c address = 30h) field descriptions (continued) i2c 30h field type reset description 6 cmp_pol r/w 0b independent comparator polarity independent comparator output polarity 0b: when cmpin is above internal threshold, cmpout is low (internal hysteresis) < default at por > 1b: when cmpin is below internal threshold, cmpout is low (external hysteresis) 5-4 cmp_deg r/w 01b independent comparator deglitch time independent comparator deglitch time, only applied to the falling edge of cmpout (high low). 00b: independent comparator is disabled 01b: independent comparator is enabled with output deglitch time 1 s < default at por > 10b: independent comparator is enabled with output deglitch time of 2 ms 11b: independent comparator is enabled with output deglitch time of 5 sec 3 force_latchoff r/w 0b force power path off when comparator triggers, charger turns off q1 and q4 (same as disable converter) so that the system is disconnected from the input source. at the same time, chrg_ok signal goes to low to notify the system. 0b: disable this function < default at por > 1b: enable this function 2 reserved r/w 0b reserved 1 en_ship_dchg r/w 0b discharge srn for shipping mode when this bit is 1, discharge srn pin down below 3.8 v in 140 ms. when 140 ms is over, this bit is reset to 0. 0b: disable shipping mode < default at por > 1b: enable shipping mode 0 auto_wakeup_en r/w 1b auto wakeup enable when this bit is high, if the battery is below minimum system voltage (reg0x 0d/0c()), the device will automatically enable 128 ma charging current for 30 mins. when the battery is charged up above minimum system voltage, charge will terminate and the bit is reset to low. 0b: disable 1b: enable < default at por >
38 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.1.3 chargeoption2 register ( i2c address = 33h/32h) [reset = 2b7] figure 25. chargeoption2 register ( i2c address = 33h/32h) [reset = 2b7] 15 14 13 12 11 10 9 8 pkpwr_tovld_deg en_pkpwr_ idpm en_pkpwr_ vsys pkpwr_ ovld_stat pkpwr_ relax_stat pkpwr_tmax[1:0] r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 en_extilim en_ichg _idchg q2_ocp acx_ocp en_acoc acoc_vth en_batoc batoc_vth r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 9. chargeoption2 register (i2c address = 33h) field descriptions i2c 33h field type reset description 7-6 pkpwr_ tovld_deg r/w 00b input overload time in peak power mode 00b: 1 ms < default at por > 01b: 2 ms 10b: 10 ms 11b: 20 ms 5 en_pkpwr_idpm r/w 0b enable peak power mode triggered by input current overshoot if reg0x33[5:4] are 00b, peak power mode is disabled. upon adapter removal, the bits are reset to 00b. 0b: disable peak power mode triggered by input current overshoot < default at por > 1b: enable peak power mode triggered by input current overshoot. 4 en_pkpwr_vsys r/w 0b enable peak power mode triggered by system voltage under-shoot if reg0x33[5:4] are 00b, peak power mode is disabled. upon adapter removal, the bits are reset to 00b. 0b: disable peak power mode triggered by system voltage under-shoot < default at por > 1b: enable peak power mode triggered by system voltage under-shoot. 3 pkpwr_ ovld_stat r/w 0b indicator that the device is in overloading cycle. write 0 to get out of overloading cycle. 0b: not in peak power mode. < default at por > 1b: in peak power mode. 2 pkpwr_ relax_stat r/w 0b indicator that the device is in relaxation cycle. write 0 to get out of relaxation cycle. 0b: not in relaxation cycle. < default at por > 1b: in relaxation mode. 1-0 pkpwr_ tmax[1:0] r/w 10b peak power mode overload and relax cycle time. when reg0x33[7:6] is programmed longer than reg0x33[1:0], there is no relax time. 00b: 5 ms 01b: 10 ms 10b: 20 ms < default at por > 11b: 40 ms
39 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated table 10. chargeoption2 register (i2c address = 32h) field descriptions i2c 32h field type reset description 7 en_extilim r/w 1b enable ilim_hiz pin to set input current limit 0b: input current limit is set by reg0x0f/0e. 1b: input current limit is set by the lower value of ilim_hiz pin and reg0x0f/0e. < default at por > 6 en_ichg _idchg r/w 0b 0b: ibat pin as discharge current. < default at por > 1b: ibat pin as charge current. 5 q2_ocp r/w 1b q2 ocp threshold by sensing q2 vds 0b: 210 mv 1b: 150 mv < default at por > 4 acx_ocp r/w 1b input current ocp threshold by sensing acp-acn. 0b: 280 mv 1b: 150 mv < default at por > 3 en_acoc r/w 0b acoc enable input overcurrent (acoc) protection by sensing the voltage across acp and acn. upon acoc (after 100- s blank-out time), converter is disabled. 0b: disable acoc < default at por > 1b: acoc threshold 125% or 200% icrit 2 acoc_vth r/w 1b acoc limit set mosfet ocp threshold as percentage of idpm with current sensed from r ac. 0b: 125% of icrit 1b: 210% of icrit < default at por > 1 en_batoc r/w 1b batoc enable battery discharge overcurrent (batoc) protection by sensing the voltage across srn and srp. upon batoc, converter is disabled. 0b: disable batoc 1b: batoc threshold 125% or 200% prochot idchg < default at por > 0 batoc_vth r/w 1b set battery discharge overcurrent threshold as percentage of prochot battery discharge current limit. 0b: 125% of prochot idchg 1b: 200% of prochot idchg < default at por >
40 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.1.4 chargeoption3 register ( i2c address = 35h/34h) [reset = 0h] figure 26. chargeoption3 register ( i2c address = 35h/34h) [reset = 0h] 15 14 13 12 11 10 9 8 en_hiz reset_reg reset_ vindpm en_otg en_ico_mod e reserved r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 reserved batfetoff_ hiz psys_otg_ idchg r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 11. chargeoption3 register (i2c address = 35h) field descriptions i2c 35h field type reset description 7 en_hiz r/w 0b device hi-z mode enable when the charger is in hi-z mode, the device draws minimal quiescent current. with vbus above uvlo. regn ldo stays on, and system powers from battery. 0b: device not in hi-z mode < default at por > 1b: device in hi-z mode 6 reset_reg r/w 0b reset registers all the registers go back to the default setting except the vindpm register. 0b: idle < default at por > 1b: reset all the registers to default values. after reset, this bit goes back to 0. 5 reset_vindpm r/w 0b reset vindpm threshold 0b: idle 1b: converter is disabled to measure vindpm threshold. after vindpm measurement is done, this bit goes back to 0 and converter starts. 4 en_otg r/w 0b otg mode enable enable device in otg mode when en_otg pin is high. 0b: disable otg < default at por > 1b: enable otg mode to supply vbus from battery. 3 en_ico_mode r/w 0b enable ico algorithm 0b: disable ico algorithm. < default at por > 1b: enable ico algorithm. 2-0 reserved r/w 0b reserved table 12. chargeoption3 register (i2c address = 34h) field descriptions i2c 34h field type reset description 7-2 reserved r/w 0b reserved 1 batfetoff_ hiz r/w 0b control batfet during hiz mode. 0b: batfet on during hi-z 1b: batfet off during hi-z 0 psys_otg_ idchg r/w 0b psys function during otg mode. 0b: psys as battery discharge power minus otg output power 1b: psys as battery discharge power only
41 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.1.5 prochotoption0 register ( i2c address = 37h/36h) [reset = 04a54h] figure 27. prochotoption0 register ( i2c address = 37h/36h) [reset = 04a54h] 15-11 10-9 8 ilim2_vth icrit_deg reserved r/w r/w r/w 7-6 5 4-3 2 1 0 vsys_vth en_prochot _ext prochot_width prochot_ clear inom_deg reserved r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 13. prochotoption0 register (i2c address = 37h) field descriptions i2c 37h field type reset description 7-3 ilim2_vth r/w 01001b i lim2 threshold 5 bits, percentage of idpm in 0x0f/0eh. measure current between acp and acn. trigger when the current is above this threshold: 00001b - 11001b: 110% - 230%, step 5% 11010b - 11110b: 250% - 450%, step 50% 11111b: out of range (ignored) default 150%, or 01001 2-1 icrit_deg r/w 01b icrit deglitch time icrit is set to be 110% of ilim2 . typical icrit deglitch time to trigger prochot. 00b: 15 s 01b: 100 s < default at por > 10b: 400 s (max 500 us) 11b: 800 s (max 1 ms) 0 reserved r/w 0b reserved table 14. prochotoption0 register (i2c address = 36h) field descriptions i2c 36h field type reset description 7-6 vsys_vth r/w 01b vsys threshold measure on vsys with fixed 20- s deglitch time. trigger when sys pin voltage is below the threshold. 00b: 5.75 v (2-4 s) or 2.85 v (1 s) 01b: 6 v (2-4 s) or 3.1 v (1 s) < default at por > 10b: 6.25 v (2-4 s) or 3.35 v (1 s) 11b: 6.5 v (2-4 s) or 3.6 v (1 s) 5 en_prochot _ext r/w 0b when pulse extension is enabled, keep the prochot pin voltage low until host writes 0x36[2] = 0. 0b: disable pulse extension < default at por > 1b: enable pulse extension 4-3 prochot _width r/w 10b prochot pulse width prochot pulse extension enable minimum prochot pulse width when reg0x36[5] = 0 00b: 100 s 01b: 1 ms 10b: 10 ms < default at por > 11b: 5 ms
42 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated table 14. prochotoption0 register (i2c address = 36h) field descriptions (continued) i2c 36h field type reset description 2 prochot _clear r/w 1b prochot pulse clear clear prochot pulse when 0x36[5] = 1. 0b: clear prochot pulse and drive prochot pin high. 1b: idle < default at por > 1 inom_deg r/w 0b inom deglitch time inom is always 10% above idpm in 0x0f/0eh. measure current between acp and acn. trigger when the current is above this threshold. 0b: 1 ms (must be max) < default at por > 1b: 50 ms (max 60 ms) 0 reserved r/w 0b reserved
43 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.1.6 prochotoption1 register ( i2c address = 39h/38h) [reset = 8120h] figure 28. prochotoption1 register ( i2c address = 39h/38h) [reset = 8120h] 15-10 9-8 idchg_vth idchg_deg r/w r/w 7 6 5 4 3 2 1 0 reserved prochot_pr ofile_ic pp_icrit pp_inom pp_idchg pp_vsys pp_batpres pp_acok r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 15. prochotoption1 register (i2c address = 39h) field descriptions i2c 39h field type reset description 7-2 idchg_vth r/w 000000b idchg threshold 6 bit, range, range 0 a to 32256 ma, step 512 ma. measure current between srn and srp. trigger when the discharge current is above the threshold. if the value is programmed to 0 ma, prochot is always triggered. default: 16384 ma or 100000 1-0 idchg_deg r/w 01b idchg deglitch time 00b: 1.6 ms 01b: 100 s < default at por > 10b: 6 ms 11b: 12 ms table 16. prochotoption1 register (i2c address = 38h) field descriptions i2c 38h field type reset description 7 reserved r/w 0b reserved 6 prochot _profile_comp r/w 0b prochot profile when all the reg0x34[6:0] bits are 0, prochot function is disabled. bit6 independent comparator 0b: disable < default at por > 1b: enable 5 prochot _profile_icrit r/w 1b 0b: disable 1b: enable < default at por > 4 prochot _profile_inom r/w 0b 0b: disable < default at por > 1b: enable 3 prochot _profile_idchg r/w 0b 0b: disable < default at por > 1b: enable 2 prochot _profile_vsys r/w 0b 0b: disable < default at por > 1b: enable 1 prochot _profile_batpres r/w 0b 0b: disable < default at por > 1b: enable (one-shot falling edge triggered) if batpres is enabled in prochot after the battery is removed, it will immediately send out one-shot prochot pulse.
44 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated table 16. prochotoption1 register (i2c address = 38h) field descriptions (continued) i2c 38h field type reset description 0 prochot _profile_acok r/w 0b 0b: disable < default at por > 1b: enable chargeoption0[15] = 0 to assert prochot pulse after adapter removal. if prochot_profile_acok is enabled in prochot after the adapter is removed, it will be pulled low.
45 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.1.7 adcoption register ( i2c address = 3b/3ah) [reset = 2000h] figure 29. adcoption register ( i2c address = 3b/3ah) [reset = 2000h] 15 14 13 12-8 adc_conv adc_start adc_ fullscale reserved r/w r/w r/w r/w 7 6 5 4 3 2 1 0 en_adc_ cmpin en_adc_ vbus en_adc_ psys en_adc_ iin en_adc_ idchg en_adc_ ichg en_adc_ vsys en_adc_ vbat r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset the adc registers are read in the following order: vbat, vsys, ichg, idchg, iin, psys, vbus, cmpin. adc is disabled in low power mode. when enabling adc, the device exit low power mode at battery only. table 17. adcoption register (i2c address = 3bh) field descriptions i2c 3bh field type reset description 7 adc_conv r/w 0b typical adc conversion time is 10 ms. 0b: one-shot update. do one set of conversion updates to registers reg0x27/26(), reg0x29/28(), reg0x2b/2a(), and reg0x2d/2c() after adc_start = 1. 1b: continuous update. do a set of conversion updates to registers reg0x27/26(), reg0x29/28(), reg0x2b/2a(), and reg0x2d/2c() every 1 sec. 6 adc_start r/w 0b 0b: no adc conversion 1b: start adc conversion. after the one-shot update is complete, this bit automatically resets to zero 5 adc_ fullscale r/w 1b adc input voltage range. when input voltage is below 5 v, or battery is 1s, full scale 2.04 v is recommended. 0b: 2.04 v 1b: 3.06 v < default at por > 4-0 reserved r/w 00000b reserved table 18. adcoption register (i2c address = 3ah) field descriptions i2c 3ah field type reset description 7 en_adc_cmpin r/w 0b 0b: disable < default at por > 1b: enable 6 en_adc_vbus r/w 0b 0b: disable < default at por > 1b: enable 5 en_adc_psys r/w 0b 0b: disable < default at por > 1b: enable 4 en_adc_iin r/w 0b 0b: disable < default at por > 1b: enable 3 en_adc_idchg r/w 0b 0b: disable < default at por > 1b: enable 2 en_adc_ichg r/w 0b 0b: disable < default at por > 1b: enable 1 en_adc_vsys r/w 0b 0b: disable < default at por > 1b: enable
46 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated table 18. adcoption register (i2c address = 3ah) field descriptions (continued) i2c 3ah field type reset description 0 en_adc_vbat r/w 0b 0b: disable < default at por > 1b: enable
47 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.2 charge and prochot status 8.6.2.1 chargerstatus register ( i2c address = 21/20h) [reset = 0000h] figure 30. chargerstatus register ( i2c address = 21/20h) [reset = 0000h] 15 14 13 12 11 10 9 8 ac_stat ico_done reserved in_vindpm in_iindpm in_fchrg in_pchrg in_otg r r r r r r r r 7 6 5 4 3 2 1 0 fault acov fault batoc fault acoc sysovp_ stat reserved fault latchoff fault_otg_ ovp fault_otg_ ocp r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 19. chargerstatus register (i2c address = 21h) field descriptions i2c 21h field type reset description 7 ac_stat r 0b input source status, same as chrg_ok bit 0b: input not present 1b: input is present 6 ico_done r 0b after the ico routine is successfully executed, the bit goes 1. 0b: ico is not complete 1b: ico is complete 5 reserved r 0b reserved 4 in_vindpm r 0b 0b: charger is not in vindpm during forward mode, or voltage regulation during otg mode 1b: charger is in vindpm during forard mode, or voltage regulation during otg mode 3 in_iindpm r 0b 0b: charger is not in iindpm 1b: charger is in iindpm 2 in_fchrg r 0b 0b: charger is not in fast charge 1b: charger is in fast charger 1 in_pchrg r 0b 0b: charger is not in pre-charge 1b: charger is in pre-charge 0 in_otg r 0b 0b: charger is not in otg 1b: charge is in otg table 20. chargerstatus register (i2c address = 20h) field descriptions i2c 20h field type reset description 7 fault acov r 0b the faults are latched until a read from host. 0b: no fault 1b: acov 6 fault batoc r 0b the faults are latched until a read from host. 0b: no fault 1b: batoc 5 fault acoc r 0b the faults are latched until a read from host. 0b: no fault 1b: acoc
48 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated table 20. chargerstatus register (i2c address = 20h) field descriptions (continued) i2c 20h field type reset description 4 sysovp_stat r 0b sysovp status and clear when the sysovp occurs, this bit is high. during the sysovp, the converter is disabled. after the sysovp is removed, the user must write a 0 to this bit or unplug the adapter to clear the sysovp condition to enable the converter again. 0b: not in sysovp < default at por > 1b: in sysovp. when sysovp is removed, write 0 to clear the sysovp latch. 3 reserved r 0b reserved 2 fault latchoff r 0b the faults are latched until a read from host. 0b: no fault 1b: latch off (reg0x30[3]) 1 fault_otg_ovp r 0b the faults are latched until a read from host. 0b: no fault 1b: otg ovp 0 fault_otg_ucp r 0b the faults are latched until a read from host. 0b: no fault 1b: otg ocp
49 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.2.2 prochotstatus register ( i2c address = 23/22h) [reset = 0h] figure 31. prochotstatus register ( i2c address = 23/22h) [reset = 0h] 15-8 reserved r 7 6 5 4 3 2 1 0 reserved stat_comp stat_icrit stat_inom stat_idchg stat_vsys stat_battery_ removal stat_adapter _removal r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 21. prochotstatus register (i2c address = 23h) field descriptions i2c 23h field type reset description ? reserved r 0b reserved table 22. prochotstatus register (i2c address = 22h) field descriptions i2c 22h field type reset description ? reserved r 0b reserved 6 stat_comp r 0b 0b: not triggered 1b: triggered 5 stat_icrit r 0b 0b: not triggered 1b: triggered 4 stat_inom r 0b 0b: not triggered 1b: triggered 3 stat_idchg r 0b 0b: not triggered 1b: triggered 2 stat_vsys r 0b 0b: not triggered 1b: triggered 1 stat_battery_removal r 0b 0b: not triggered 1b: triggered 0 stat_adapter_removal r 0b 0b: not triggered 1b: triggered
50 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.3 chargecurrent register ( i2c address = 03/02h) [reset = 0h] to set the charge current, write a 16-bit chargecurrent() command (reg0x 03/02()) using the data format listed in table 23 and table 24 . with 10-m sense resistor, the charger provides charge current range of 64 ma to 8.128 a, with a 64-ma step resolution. upon por, chargecurrent() is 0 a. any conditions for chrg_ok low except acov will reset chargecurrent() to zero. cell_batpresz going low (battery removal) will reset the chargecurrent() register to 0 a. charge current is not reset in acoc, tshut, power path latch off (reg0x30[1]), and sysovp. a 0.1- f capacitor between srp and srn for differential mode filtering is recommended; an optional 0.1- f capacitor between srn and ground, and an optional 0.1- f capacitor between srp and ground for common mode filtering. meanwhile, the capacitance on srp should not be higher than 0.1 f in order to properly sense the voltage across srp and srn for cycle-by-cycle current detection. the srp and srn pins are used to sense voltage drop across rsr with default value of 10 m . however, resistors of other values can also be used. for a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss. if current sensing resistor value is too high, it may trigger an over current protection threshold because the current ripple voltage is too high. in such a case, either a higher inductance value or a lower current sensing resistor value should be used to limit the current ripple voltage level. a current sensing resistor value no more than 20 m is suggested. figure 32. chargecurrent register with 10-m sense resistor ( i2c address = 03/02h) [reset = 0h] 15 14 13 12 11 10 9 8 reserved charge current, bit 6 charge current, bit 5 charge current, bit 4 charge current, bit 3 charge current, bit 2 r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 charge current, bit 1 charge current, bit 0 reserved reserved r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 23. charge current register (14h) with 10-m sense resistor (i2c address = 03h) field descriptions i2c 03h field type reset description 7-5 reserved r/w 000b not used. 1 = invalid write. 4 charge current, bit 6 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 4096 ma of charger current. 3 charge current, bit 5 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 2048 ma of charger current. 2 charge current, bit 4 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 1024 ma of charger current. 1 charge current, bit 3 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 512 ma of charger current. 0 charge current, bit 2 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 256 ma of charger current. table 24. charge current register (14h) with 10-m sense resistor (i2c address = 02h) field descriptions i2c 02h field type reset description 7 charge current, bit 1 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 128 ma of charger current.
51 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated table 24. charge current register (14h) with 10-m sense resistor (i2c address = 02h) field descriptions (continued) i2c 02h field type reset description 6 charge current, bit 0 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 64 ma of charger current. 5-0 reserved r/w 000000b not used. value ignored. 8.6.3.1 battery pre-charge current clamp during pre-charge, batfet works in linear mode or ldo mode (default reg0x 00[2] = 1). for 2-4 cell battery, the system is regulated at minimum system voltage in reg0x 0d/0c() and the pre-charge current is clamped at 384 ma. for 1 cell battery, the pre-charge to fast charge threshold is 3 v, and the pre-charge current is clamped at 384 ma. however, the batfet stays in ldo mode operation till battery voltage is above minimum system voltage (~3.6 v). during battery voltage from 3 v to 3.6 v, the fast charge current is clamped at 2 a.
52 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.4 maxchargevoltage register ( i2c address = 05/04h) [reset value based on cell_batpresz pin setting] to set the output charge voltage, write a 16-bit chargevoltage register command (reg0x 05/04()) using the data format listed in table 25 and table 26 . the charger provides charge voltage range from 1.024 v to 19.200 v, with 16-mv step resolution. any write below 1.024 v or above 19.200 v is ignored. upon por or when charge is disabled, the system is regulated at the maxchargevoltage register. upon por, reg0x 05/04() is by default set as 4192 mv for 1 s, 8400 mv for 2 s, 12592 mv for 3 s or 16800 mv for 4 s. after chrg_ok, if host writes reg0x 03/02() before reg0x 05/04(), the charge will start after the write to reg0x 03/02().if the battery is different from 4.2 v/cell, the host has to write to reg0x 05/04() before reg0x 03/02() for correct battery voltage setting. writing reg0x 05/04() to 0 will set reg0x 05/04() to default value on cell_batpresz pin, and force reg0x 03/02() to zero to disable charge. the srn pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, and directly place a decoupling capacitor (0.1 f recommended) as close to the device as possible to decouple high frequency noise. figure 33. maxchargevoltage register ( i2c address = 05/04h) [reset value based on cell_batpresz pin setting] 15 14 13 12 11 10 9 8 reserved max charge voltage, bit 10 max charge voltage, bit 9 max charge voltage, bit 8 max charge voltage, bit 7 max charge voltage, bit 6 max charge voltage, bit 5 max charge voltage, bit 4 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 max charge voltage, bit 3 max charge voltage, bit 2 max charge voltage, bit 1 max charge voltage, bit 0 reserved r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 25. maxchargevoltage register (i2c address = 05h) field descriptions i2c 05h field type reset description 7 reserved r/w 0b not used. 1 = invalid write. 6 max charge voltage, bit 10 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 16384 mv of charger voltage. 5 max charge voltage, bit 9 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 8192 mv of charger voltage 4 max charge voltage, bit 8 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 4096 mv of charger voltage. 3 max charge voltage, bit 7 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 2048 mv of charger voltage. 2 max charge voltage, bit 6 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 1024 mv of charger voltage. 1 max charge voltage, bit 5 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 512 mv of charger voltage. 0 max charge voltage, bit 4 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 256 mv of charger voltage. table 26. maxchargevoltage register (i2c address = 04h) field descriptions i2c 04h field type reset description 7 max charge voltage, bit 3 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 128 mv of charger voltage.
53 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated table 26. maxchargevoltage register (i2c address = 04h) field descriptions (continued) i2c 04h field type reset description 6 max charge voltage, bit 2 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 64 mv of charger voltage. 5 max charge voltage, bit 1 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 32 mv of charger voltage. 4 max charge voltage, bit 0 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 16 mv of charger voltage. 3-0 reserved r/w 0000b not used. value ignored.
54 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.5 minsystemvoltage register ( i2c address = 0d/0ch) [reset value based on cell_batpresz pin setting] to set the minimum system voltage, write a 16-bit minsystemvoltage register command (reg0x 0d/0c()) using the data format listed in table 27 and table 28 . the charger provides minimum system voltage range from 1.024 v to 16.128 v, with 256-mv step resolution. any write below 1.024 v or above 16.128 v is ignored. upon por, the minsystemvoltage register is 3.584 v for 1 s, 6.144 v for 2 s and 9.216 v for 3 s, and 12.288 v for 4 s. figure 34. minsystemvoltage register ( i2c address = 0d/0ch) [reset value based on cell_batpresz pin setting] 15 14 13 12 11 10 9 8 reserved min system voltage, bit 5 min system voltage, bit 4 min system voltage, bit 3 min system voltage, bit 2 min system voltage, bit 1 min system voltage, bit 0 r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 reserved r/w legend: r/w = read/write; r = read only; -n = value after reset table 27. minsystemvoltage register (i2c address = 0dh) field descriptions i2c 0dh field type reset description 7-6 reserved r/w 00b not used. 1 = invalid write. 5 min system voltage, bit 5 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 8192 mv of system voltage. 4 min system voltage, bit 4 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 4096mv of system voltage. 3 min system voltage, bit 3 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 2048 mv of system voltage. 2 min system voltage, bit 2 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 1024 mv of system voltage. 1 min system voltage, bit 1 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 512 mv of system voltage. 0 min system voltage, bit 0 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 256 mv of system voltage. table 28. minsystemvoltage register (i2c address = 0ch) field descriptions i2c 0ch field type reset description 7-0 reserved r/w 0000000 0b not used. value ignored. 8.6.5.1 system voltage regulation the device employs narrow vdc architecture (nvdc) with batfet separating system from battery. the minimum system voltage is set by reg0x 0d/0c(). even with a deeply depleted battery, the system is regulated above the minimum system voltage with batfet. when the battery is below minimum system voltage setting, the batfet operates in linear mode (ldo mode), and the system is regulated above the minimum system voltage setting. as the battery voltage rises above the minimum system voltage, batfet is fully on when charging or in supplement mode and the voltage difference between the system and battery is the vds of batfet. system voltage is regulated 160 mv above battery voltage when batfet is off (no charging or no supplement current). when batfet is removed, the system node vsys is shorted to srp. before the converter starts operation, ldo mode needs to be disabled. the following sequence is required to configure charger without batfet. 1. before adapter plugs in, put the charger into hiz mode. (either pull pin 6 ilim_hiz to ground, or set
55 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated reg0x 35[7] to 1) 2. set 0x 00[2] to 0 to disable ldo mode. 3. set 0x30[0] to 0 to disable auto-wakeup mode. 4. check if battery voltage is properly programmed (reg0x 05/04) 5. set pre-charge/charge current (reg0x 03/02) 6. put the device out of hiz mode. (release ilim_hiz from ground and set reg0x 35[7]=0). in order to prevent any accidental sw mistakes, the host sets low input current limit (a few hundred milliamps) when device is out of hiz. 8.6.6 input current and input voltage registers for dynamic power management the charger supports dynamic power management (dpm). normally, the input power source provides power for the system load or to charge the battery. when the input current exceeds the input current setting, or the input voltage falls below the input voltage setting, the charger decreases the charge current to provide priority to the system load. as the system current rises, the available charge current drops accordingly toward zero. if the system load keeps increasing after the charge current drops down to zero, the system voltage starts to drop. as the system voltage drops below the battery voltage, the battery will discharge to supply the heavy system load. 8.6.6.1 input current registers to set the maximum input current limit, write a 16-bit iin_host register command (reg0x 0f/0e()) using the data format listed in table 29 and table 30 . when using a 10-m sense resistor, the charger provides an input- current limit range of 50 ma to 6400 ma, with 50-ma resolution. the default current limit is 3.3 a. due to the usb current setting requirement, the register setting specifies the maximum current instead of the typical current. upon adapter removal, the input current limit is reset to the default value of 3.3 a. the register offset is 50 ma. with code 0, the input current limit is 50 ma. the acp and acn pins are used to sense r ac with the default value of 10 m . however, resistors of other values can also be used. for a larger sense resistor, a larger sense voltage is given and a higher regulation accuracy, but at the expense of higher conduction loss. instead of using the internal dpm loop, the user can build up an external input current regulation loop and have the feedback signal on the ilim_hiz pin. (2) in order to disable ilim_hiz pin, the host can write to 0x 32[7] to disable ilim_hiz pin, or pull ilim_hiz pin above 4.0 v. ( ) ilim _ hiz acp acn dpm ac v 1v 40 v v 1 40 i r = + - = +
56 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.6.1.1 iin_host register with 10-m sense resistor ( i2c address = 0f/0eh) [reset = 4000h] figure 35. iin_host register with 10-m sense resistor ( i2c address = 0f/0eh) [reset = 4100h] 15 14 13 12 11 10 9 8 reserved input current set by host, bit 6 input current set by host, bit 5 input current set by host, bit 4 input current set by host, bit 3 input current set by host, bit 2 input current set by host, bit 1 input current set by host, bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 reserved r legend: r/w = read/write; r = read only; -n = value after reset table 29. iin_host register with 10-m sense resistor (i2c address = 0fh) field descriptions i2c 0fh field type reset description 7 reserved r/w 0b not used. 1 = invalid write. 6 input current set by host, bit 6 r/w 1b 0 = adds 0 ma of input current. 1 = adds 3200 ma of input current. 5 input current set by host, bit 5 r/w 0b 0 = adds 0 ma of input current. 1 = adds 1600 ma of input current. 4 input current set by host, bit 4 r/w 0b 0 = adds 0 ma of input current. 1 = adds 800 ma of input current. 3 input current set by host, bit 3 r/w 0b 0 = adds 0 ma of input current. 1 = adds 400 ma of input current. 2 input current set by host, bit 2 r/w 0b 0 = adds 0 ma of input current. 1 = adds 200 ma of input current. 1 input current set by host, bit 1 r/w 0b 0 = adds 0 ma of input current. 1 = adds 100 ma of input current. 0 input current set by host, bit 0 r/w 0b 0 = adds 0 ma of input current. 1 = adds 50 ma of input current. table 30. iin_host register with 10-m sense resistor (i2c address = 0eh) field descriptions i2c 0eh field type reset description 7-0 reserved r 0000000 0b not used. value ignored.
57 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.6.1.2 iin_dpm register with 10-m sense resistor ( i2c address = 25/24h) [reset = 0h] iin_dpm register reflects the actual input current limit programmed in the register, either from host or from ico. after ico, the current limit used by dpm regulation may differ from the iin_host register settings. the actual dpm limit is reported in reg0x 25/24(). the register offset is 50 ma. with code 0, the input current limit read- back is 50 ma. figure 36. iin_dpm register with 10-m sense resistor ( i2c address = 25/24h) [reset = 0h] 15 14 13 12 11 10 9 8 reserved input current in dpm, bit 6 input current in dpm, bit 5 input current in dpm, bit 4 input current in dpm, bit 3 input current in dpm, bit 2 input current in dpm, bit 1 input current in dpm, bit 0 r r r r r r r r 7 6 5 4 3 2 1 0 reserved r legend: r/w = read/write; r = read only; -n = value after reset table 31. iin_dpm register with 10-m sense resistor (i2c address = 25h) field descriptions i2c 25h field type reset description 7 reserved r 0b not used. 1 = invalid write. 6 input current in dpm, bit 6 r 0b 0 = adds 0 ma of input current. 1 = adds 3200 ma of input current. 5 input current in dpm, bit 5 r 0b 0 = adds 0 ma of input current. 1 = adds 1600 ma of input current. 4 input current in dpm, bit 4 r 0b 0 = adds 0 ma of input current. 1 = adds 800ma of input current 3 input current in dpm, bit 3 r 0b 0 = adds 0 ma of input current. 1 = adds 400 ma of input current. 2 input current in dpm, bit 2 r 0b 0 = adds 0 ma of input current. 1 = adds 200 ma of input current. 1 input current in dpm, bit 1 r 0b 0 = adds 0 ma of input current. 1 = adds 100 ma of input current. 0 input current in dpm, bit 0 r 0b 0 = adds 0 ma of input current. 1 = adds 50 ma of input current. table 32. iin_dpm register with 10-m sense resistor (i2c address = 24h) field descriptions i2c 24h field type reset description 7-0 reserved r 00000000b not used. value ignored.
58 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.6.1.3 inputvoltage register ( i2c address = 0b/0ah) [reset = vbus-1.28v] to set the input voltage limit, write a 16-bit inputvoltage register command (reg0x 0b/0a()) using the data format listed in table 33 and table 34 . if the input voltage drops more than the inputvoltage register allows, the device enters dpm and reduces the charge current. the default offset voltage is 1.28 v below the no-load vbus voltage. the dc offset is 3.2 v (0000000). figure 37. inputvoltage register ( i2c address = 0b/0ah) [reset = vbus-1.28v] 15 14 13 12 11 10 9 8 reserved input voltage, bit 7 input voltage, bit 6 input voltage, bit 5 input voltage, bit 4 input voltage, bit 3 input voltage, bit 2 r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 input voltage, bit 1 input voltage, bit 0 reserved r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 33. inputvoltage register (i2c address = 0bh) field descriptions i2c 0bh field type reset description 7-6 reserved r/w 00b not used. 1 = invalid write. 5 input voltage, bit 7 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 8192 mv of input voltage. 4 input voltage, bit 6 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 4096mv of input voltage. 3 input voltage, bit 5 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 2048 mv of input voltage. 2 input voltage, bit 4 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 1024 mv of input voltage. 1 input voltage, bit 3 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 512 mv of input voltage. 0 input voltage, bit 2 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 256 mv of input voltage. table 34. inputvoltage register (i2c address = 0ah) field descriptions i2c 0ah field type reset description 7 input voltage, bit 1 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 128 mv of input voltage. 6 input voltage, bit 0 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 64 mv of input voltage 5-0 reserved r/w 000000b not used. value ignored.
59 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.7 otgvoltage register ( i2c address = 07/06h) [reset = 0h] to set the otg output voltage limit, write to reg0x 07/06() using the data format listed in table 35 and table 36 . the dc offset is 4.48 v (0000000). figure 38. otgvoltage register ( i2c address = 07/06h) [reset = 0h] 15 14 13 12 11 10 9 8 reserved otg voltage, bit 7 otg voltage, bit 6 otg voltage, bit 5 otg voltage, bit 4 otg voltage, bit 3 otg voltage, bit 2 r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 otg voltage, bit 1 otg voltage, bit 0 reserved r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 35. otgvoltage register (i2c address = 07h) field descriptions i2c 07h field type reset description 7-6 reserved r/w 00b not used. 1 = invalid write. 5 otg voltage, bit 7 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 8192 mv of otg voltage. 4 otg voltage, bit 6 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 4096 mv of otg voltage. 3 otg voltage, bit 5 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 2048 mv of otg voltage. 2 otg voltage, bit 4 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 1024 mv of otg voltage. 1 otg voltage, bit 3 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 512 mv of otg voltage. 0 otg voltage, bit 2 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 256 mv of otg voltage. table 36. otgvoltage register (i2c address = 06h) field descriptions i2c 06h field type reset description 7 otg voltage, bit 1 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 128 mv of otg voltage. 6 otg voltage, bit 0 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 64 mv of otg voltage. 5-0 reserved r/w 000000b not used. value ignored.
60 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.8 otgcurrent register ( i2c address = 09/08h) [reset = 0h] to set the otg output current limit, write to reg0x 09/08() using the data format listed in table 37 and table 38 . figure 39. otgcurrent register ( i2c address = 09/08h) [reset = 0h] 15 14 13 12 11 10 9 8 reserved otg current set by host, bit 6 otg current set by host, bit 5 otg current set by host, bit 4 otg current set by host, bit 3 otg current set by host, bit 2 otg current set by host, bit 1 otg current set by host, bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 reserved r/w legend: r/w = read/write; r = read only; -n = value after reset table 37. otgcurrent register (i2c address = 09h) field descriptions i2c 09h field type reset description 7 reserved r/w 0b not used. 1 = invalid write. 6 otg current set by host, bit 6 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 3200 ma of otg current. 5 otg current set by host, bit 5 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 1600ma of otg current. 4 otg current set by host, bit 4 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 800 ma of otg current. 3 otg current set by host, bit 3 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 400 ma of otg current. 2 otg current set by host, bit 2 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 200 ma of otg current. 1 otg current set by host, bit 1 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 100 ma of otg current. 0 otg current set by host, bit 0 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 50 ma of otg current. table 38. otgcurrent register (i2c address = 08h) field descriptions i2c 08h field type reset description 7-0 reserved r/w 00000000b not used. value ignored.
61 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.9 adcvbus/psys register ( i2c address = 27h) ? psys: full range: 3.06 v, lsb: 12 mv ? vbus: full range: 3200 mv to 19520 mv, lsb: 64 mv figure 40. adcvbus/psys register ( i2c address = 27h) 15 14 13 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 39. adcvbus/psys register field descriptions bit field type reset description 15-8 r 8-bit digital output of input voltage 7-0 r 8-bit digital output of system power
62 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.10 adcibat register ( i2c address = 29h) ? ichg: full range: 8.128 a, lsb 64: ma ? idchg: full range: 32.512 a, lsb: 256 ma figure 41. adcibat register ( i2c address = 29h) 15 14 13 12 11 10 9 8 reserved r r r r r r r 7 6 5 4 3 2 1 0 reserved r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 40. adcibat register field descriptions bit field type reset description 15 reserved r not used. value ignored. 14-8 r 7-bit digital output of battery charge current 7 reserved r not used. value ignored. 6-0 r 7-bit digital output of battery discharge current
63 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.11 adciincmpin register ( i2c address = 2bh) ? iin: full range: 12.75 a, lsb: 50 ma ? cmpin: full range: 3.06 v, lsb: 12 mv figure 42. adciincmpin register ( i2c address = 2bh) 15 14 13 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 41. adciincmpin register field descriptions bit field type reset description 15-8 r 8-bit digital output of input current 7-0 r 8-bit digital output of cmpin voltage
64 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.12 adcvsysvbat register ( i2c address = 2dh) (reset = ) ? vsys: full range: 2.88 v to 19.2 v, lsb: 64 mv ? vbat: full range: 2.88 v to 19.2 v, lsb: 64 mv figure 43. adcvsysvbat register ( i2c address = 2dh) (reset = ) 15 14 13 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 42. adcvsysvbat register field descriptions bit field type reset description 15-8 r 8-bit digital output of system voltage 7-0 r 8-bit digital output of battery voltage
65 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.13 id registers 8.6.13.1 manufactureid register ( i2c address = 2eh) [reset = 0040h] figure 44. manufactureid register ( i2c address = 2eh) [reset = 0040h] 15-0 manufacture_id r legend: r/w = read/write; r = read only; -n = value after reset table 43. manufactureid register field descriptions i2c 2eh field type reset description (read only) 7-0 manufacture_id r 40h 8.6.13.2 device id (deviceaddress) register ( i2c address = 2fh) [reset = 0h] figure 45. device id (deviceaddress) register ( i2c address = 2fh) [reset = 0h] 15-8 reserved r 7-0 device_id r legend: r/w = read/write; r = read only; -n = value after reset table 44. device id (deviceaddress) register field descriptions i2c 2fh field type reset description (read only) 15-8 reserved r 0b reserved 7-0 device_id r 0b i2c: 78h
66 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated (1) refer to adapter specification for settings for input voltage and input current limit. (2) refer to battery specification for settings. 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the bq2570xevm-732 evaluation module (evm) is a complete charger module for evaluating the BQ25703A. the application curves were taken using the bq2570xevm-732. refer to the evm user's guide ( sluubg6 ) for evm information. 9.2 typical application figure 46. application diagram 9.2.1 design requirements design parameter example value input voltage (1) 3.5 v < adapter voltage < 24 v input current limit (1) 3.2 a for 65 w adapter battery charge voltage (2) 8400 mv for 2s battery BQ25703A acn vbus hidrv1 srn iadpt ibat psys adapter vsys batt btst1 btst2 lodrv1 sw1 sw2 lodrv2 hidrv2 srp /batdrv vdda comp1 comp2 sda scl 3.3v or 1.8v chrg_ok cell_batpresz 1.05v /prochot acp sys host (i2c) q1 q2 q3 q4 regn gnd ilim_hiz en_otg r ac =10m : 2.2 3.3uf 1uf regn 10 : 50 : 10k : 10k : 10k : 100pf 100pf 30k : vdda 250k : 350k : to cpu 47nf 47nf 4x10 p f : 1 p f 6x10 p f optional snubber 10k : cmpout cmpin r sr =10m : 10nf 2.2uh 137k : 1 : 470nf 15nf 15nf 10 : 10 : copyright ? 2017, texas instruments incorporated
67 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated typical application (continued) design parameter example value battery charge current (2) 3072 ma for 2s battery minimum system voltage (2) 614 mv for 2s battery 9.2.2 detailed design procedure the parameters are configurable using the evaluation software. the simplified application circuit (see figure 46 , as the application diagram) shows the minimum component requirements. inductor, capacitor, and mosfet selection are explained in the rest of this section. refer to the evm user's guide ( sluubg6 ) for the complete application schematic. 9.2.2.1 input snubber and filter for voltage spike damping during adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second order system. the voltage spike at vbus pin maybe beyond ic maximum voltage rating and damage ic. the input filter must be carefully designed and tested to prevent over voltage event on vbus pin. there are several methods to damp or limit the over voltage spike during adapter hot plug-in. an electrolytic capacitor with high esr as an input capacitor can damp the over voltage spike well below the ic maximum pin voltage rating. a high current capability tvs zener diode can also limit the over voltage level to an ic safe level. however these two solutions may not have low cost or small size. a cost effective and small size solution is shown in figure 47 . the r1 and c1 are composed of a damping rc network to damp the hot plug-in oscillation. as a result the over voltage spike is limited to a safe level. d1 is used for reverse voltage protection for vbus pin. c2 is vbus pin decoupling capacitor and it should be placed as close as possible to vbus pin. c2 value should be less than c1 value so r1 can dominate the equivalent esr value to get enough damping effect. r2 is used to limit inrush current of d1 to prevent d1 getting damage when adapter hot plug-in. r2 and c2 should have 10 s time constant to limit the dv/dt on vbus pin to reduce inrush current when adapter hot plug in. r1 has high inrush current. r1 package must be sized enough to handle inrush current power loss according to resistor manufacturer ? s data sheet. the filter components' value always need to be verified with real application and minor adjustments may need to fit in the real application circuit. figure 47. input filter 9.2.2.2 acp-acn input filter the BQ25703A has average current mode control. the input current sensing through acp/acn is critical to recover inductor current ripple. parasitic inductance on board will generate high frequency ringing on acp-acn which overwhelms converter sensed inductor current information, so it is difficult to manage parasitic inductance created based on different pcb layout. bigger parasitic inductance will generate bigger sense current ringing which will cause the average current control loop to go into oscillation. for real system board condition, we suggest to use below circuit design to get best result and filter noise induced from different pcb parasitic factor. with time constant of filter from 47 nsec to 200 nsec, the filtering on ringing is effective and in the meantime, the delay of on the sensed signal is small and therefore poses no concern for average current mode control. r1(2010) 2 w c1 2.2 f m d1 c2 0.47-1 f m r2(0805)1 w adapterconnector vbus pin
68 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated figure 48. acn-acp input filter 9.2.2.3 inductor selection the BQ25703A has two selectable fixed switching frequency. higher switching frequency allows the use of smaller inductor and capacitor values. inductor saturation current should be higher than the charging current (i chg ) plus half the ripple current (i ripple ): (3) the inductor ripple current in buck operation depends on input voltage (v in ), duty cycle (d buck = v out /v in ), switching frequency (f s ) and inductance (l): (4) during boost operation, the duty cycle is: d boost = 1 ? (v in /v bat ) and the ripple current is: i ripple_boost = (vin d boost ) / (f s l) the maximum inductor ripple current happens with d = 0.5 or close to 0.5. for example, the battery charging voltage range is from 9 v to 12.6 v for 3-cell battery pack. for 20-v adapter voltage, 10-v battery voltage gives the maximum inductor ripple current. another example is 4-cell battery, the battery voltage range is from 12 v to 16.8 v, and 12-v battery voltage gives the maximum inductor ripple current. usually inductor ripple is designed in the range of (20 ? 40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. 9.2.2.4 input capacitor input capacitor should have enough ripple current rating to absorb input switching ripple current. the worst case rms ripple current is half of the charging current when duty cycle is 0.5 in buck mode. if the converter does not operate at 50% duty cycle, then the worst case capacitor rms current occurs where the duty cycle is closest to 50% and can be estimated by equation 5 : (5) sat chg ripple i i + (1/2) i 3 rac acp acn r acp 10ohm r acn 10ohm c acp 15nf c acn 15nf bq2570x c diff open 4~6x10uf (0805) 1nf+10nf (0402) hidrv1 q1 copyright ? 2017, texas instruments incorporated cin chg i = i d (1 d) - in ripple_buck s v d (1 d) i = l - f
69 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated low esr ceramic capacitor such as x7r or x5r is preferred for input decoupling capacitor and should be placed to the drain of the high side mosfet and source of the low side mosfet as close as possible. voltage rating of the capacitor must be higher than normal input voltage level. 25 v rating or higher capacitor is preferred for 19 v - 20 v input voltage. minimum 4 - 6 pcs of 10- f 0805 size capacitor is suggested for 45 - 65 w adapter design. ceramic capacitors show a dc-bias effect. this effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. the effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. see the manufacturer's datasheet about the performance with a dc bias voltage applied. it may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. 9.2.2.5 output capacitor output capacitor also should have enough ripple current rating to absorb output switching ripple current. in buck mode the output capacitor rms current is given: to get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 10 khz and 20 khz. the preferred ceramic capacitor is 25-v x7r or x5r for output capacitor. minimum 6 pcs of 10- f 0805 size capacitor is suggested to be placed by the inductor. place the capacitors after q4 drain. place minimum 10 f after the charge current sense resistor for best stability. ceramic capacitors show a dc-bias effect. this effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. the effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. see the manufacturer's data sheet about the performance with a dc bias voltage applied. it may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. 9.2.2.6 power mosfets selection four external n-channel mosfets are used for a synchronous switching battery charger. the gate drivers are internally integrated into the ic with 6 v of gate drive voltage. 30 v or higher voltage rating mosfets are preferred for 19 v - 20 v input voltage. figure-of-merit (fom) is usually used for selecting proper mosfet based on a tradeoff between the conduction loss and switching loss. for the top side mosfet, fom is defined as the product of a mosfet's on-resistance, r ds(on) , and the gate-to-drain charge, q gd . for the bottom side mosfet, fom is defined as the product of the mosfet's on-resistance, r ds(on) , and the total gate charge, q g . fom top = r ds(on) x q gd ; fom bottom = r ds(on) x q g (6) the lower the fom value, the lower the total power loss. usually lower r ds(on) has higher cost with the same package size. the top-side mosfet loss includes conduction loss and switching loss. it is a function of duty cycle (d=v out /v in ), charging current (i chg ), mosfet's on-resistance (r ds(on) ), input voltage (v in ), switching frequency (f s ), turn on time (t on ) and turn off time (t off ): (7) the first item represents the conduction loss. usually mosfet r ds(on) increases by 50% with 100 c junction temperature rise. the second term represents the switching loss. the mosfet turn-on and turn-off times are given by: (8) where q sw is the switching charge, i on is the turn-on gate driving current and i off is the turn-off gate driving current. if the switching charge is not given in mosfet datasheet, it can be estimated by gate-to-drain charge (q gd ) and gate-to-source charge (q gs ): (9) gate driving current can be estimated by regn voltage (v regn ), mosfet plateau voltage (v plt ), total turn-on gate resistance (r on ) and turn-off gate resistance (r off ) of the gate driver: sw gd gs 1 q = q + q 2 sw sw on off on off q q t = , t = i i 2 top chg ds(on) in chg on off s 1 p = d i r + v i (t + t ) 2 f
70 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated (10) the conduction loss of the bottom-side mosfet is calculated with the following equation when it operates in synchronous continuous conduction mode: p bottom = (1 - d) x i chg 2 x r ds(on) (11) when charger operates in non-synchronous mode, the bottom-side mosfet is off. as a result all the freewheeling current goes through the body-diode of the bottom-side mosfet. the body diode power loss depends on its forward voltage drop (v f ), non-synchronous mode charging current (i nonsync ), and duty cycle (d). p d = v f x i nonsync x (1 - d) (12) the maximum charging current in non-synchronous mode can be up to 0.25 a for a 10-m charging current sensing resistor or 0.5 a if battery voltage is below 2.5 v. the minimum duty cycle happens at lowest battery voltage. choose the bottom-side mosfet with either an internal schottky or body diode capable of carrying the maximum non-synchronous mode charging current. 9.2.3 application curves 2-cell without battery figure 49. power up from 20 v 2-cell without battery figure 50. power up from 5 v 3-cell vbat = 10 v figure 51. power off from 12 v vbus 5 v to 20 v figure 52. system regulation ch1: vbus ch2: sw1 ch3: sw2 ch4: il ch1: vbus ch2: sw1 ch3: sw2 ch4: vsys with 9vos ch1: vbus ch2: vdda ch3: chrg_ok ch4: vsys ch1: vbus ch2: vdda ch3: chrg_ok ch4: vsys regn plt plt on off on off v - v v i = , i = r r
71 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated vbus = 20 v, vsys = 10 v, isys = 200 ma figure 53. pfm operation figure 54. pwm operation vbus = 5 v, vbat = 10 v figure 55. switching during boost mode vbus = 12 v, vbat = 12 v figure 56. switching during buck boost mode vbus = 12 v/3.3 a, 3-cell, vsys = 9 v, without battery figure 57. system regulation in buck mode vbus = 9 v/3.3 a, 3-cell, vsys = 9 v, without battery figure 58. system regulation in buck boost mode ch1: vsys ch2: iin ch3: isys ch1: hidrv2 ch2: sw2 ch3: lodrv2 ch4: il ch2: sw1 ch3: sw2 ch4: il ch2: sw1 ch3: sw2 ch4: il ch1: hidrv1 ch2: sw1 ch3: lodrv1 ch1: il ch1: vsys ch2: iin ch3: isys
72 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated vbus = 5 v/3.3 a, 3-cell, vsys = 9 v, without battery figure 59. system regulation in boost mode vbus = 20 v/3.3 v, vbat = 7.5 v figure 60. input current regulation in buck mode vbus = 5 v/3.3 v, vbat = 7.5 v figure 61. input current in boost mode vbus = 5 v figure 62. otg power up from 8 v battery vbat = 10 v, vbus 5 v to 20 v, iotg = 500 ma figure 63. otg voltage ramp up figure 64. otg power off ch1: scl ch2: vbus ch3: sw2 ch1: scl ch2: vbus ch3: sw2 ch2:iin ch3:isys ch4:ibat ch1: en_otg ch2: vbus ch1: vsys ch2: iin ch3: isys ch2: iin ch3: isys ch4: ibat
73 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated vbat = 10 v, vbus = 20 v figure 65. otg load transient ch2: vbus ch3: ivbus
74 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 10 power supply recommendations the valid adapter range is from 3.5 v ( v vbus_conven ) to 24 v (acov) with at least 500-ma current rating. when chrg_ok goes high, the system is powered from adapter through the charger. when adapter is removed, the system is connected to battery through batfet. typically the battery depletion threshold should be greater than the minimum system voltage so that the battery capacity can be fully utilized for maximum battery life.
75 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 layout 11.1 layout guidelines the switching node rise and fall times should be minimized for minimum switching loss. proper layout of the components to minimize high frequency current path loop (see layout example section) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. here is a pcb layout priority list for proper layout. layout pcb according to this specific order is essential. 1. place the input capacitor as close as possible to the supply of the switching mosfet and ground connections. use a short copper trace connection. these parts must be placed on the same layer of pcb using vias to make this connection. 2. the device must be placed close to the gate pins of the switching mosfet. keep the gate drive signal traces short for a clean mosfet drive. the device can be placed on the other side of the pcb of switching mosfets. 3. place an inductor input pin as close as possible to the output pin of the switching mosfet. minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. do not use multiple layers in parallel for this connection. minimize parasitic capacitance from this area to any other trace or plane. 4. the charging current sensing resistor should be placed right next to the inductor output. route the sense leads connected across the sensing resistor back to the device in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see figure 67 for kelvin connection for best current accuracy). place a decoupling capacitor on these traces next to the device. 5. place an output capacitor next to the sensing resistor output and ground. 6. output capacitor ground connections must be tied to the same copper that connects to the input capacitor ground before connecting to system ground. 7. use a single ground connection to tie the charger power ground to the charger analog ground. just beneath the device, use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling. 8. route analog ground separately from power ground. connect analog ground and connect power ground separately. connect analog ground and power ground together using power pad as the single ground connection point. or using a 0- resistor to tie analog ground to power ground (power pad should tie to analog ground in this case if possible). 9. decoupling capacitors must be placed next to the device pins. make trace connection as short as possible. 10. it is critical that the exposed power pad on the backside of the device package be soldered to the pcb ground. 11. the via size and number should be enough for a given current path. see the evm design ( sluubg6 ) for the recommended component placement with trace and via locations. for wqfn information, see slua271 . 11.2 layout example 11.2.1 layout consideration of current path figure 66. high frequency current path high frequency current path l1 r1 c2 c1 gnd phase v bat bat v in
76 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated layout example (continued) 11.2.2 layout consideration of short circuit protection figure 67. sensing resistor pcb layout charge current direction to srp and srn pin r sns to inductor to capacitor and battery current sensing direction
77 BQ25703A www.ti.com sluscu1 ? may 2017 submit documentation feedback copyright ? 2017, texas instruments incorporated 12 device and documentation support 12.1 device support 12.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 12.2 documentation support 12.2.1 related documentation for related documentation see the following: ? semiconductor and ic package thermal metrics application report spra953 ? bq2570x evaluation module user's guide sluubg6 ? qfn/son pcb attachment application report slua271 12.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.5 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.6 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
78 BQ25703A sluscu1 ? may 2017 www.ti.com submit documentation feedback copyright ? 2017, texas instruments incorporated 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 24-may-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples BQ25703Arsnr preview qfn rsn 32 3000 tbd call ti call ti -40 to 85 BQ25703Arsnt preview qfn rsn 32 250 tbd call ti call ti -40 to 85 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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